公开(公告)号：US20050182809A1

公开(公告)日：2005-08-18

申请号：US11106109

申请日：2005-04-14

申请人： Steven Robinson ,  William Chren

发明人： Steven Robinson ,  William Chren

IPC分类号： G06F5/01 ,  G06F7/38 ,  G06F7/72

CPC分类号： G06F7/729 ,  G06F5/01

摘要： A modulo mi adder and a modulo mi,j scaling unit for use with an RNS. The adder includes a modulo mi barrel shifter, and a dynamic storage unit coupled to the barrel shifter to store the output of the barrel shifter. In a preferred embodiment, the dynamic storage unit includes one dynamic latch for each output line of the barrel shifter, with each of the dynamic latches including a clocked inverter in cascade with an inverter. One modulo mi,j scaling unit includes a modified modulo mi barrel shifter that performs both residue conversion and an arithmetic operation. The residue conversion is performed without using combinational logic. In one preferred embodiment, the modified barrel shifter performs the residue conversion though mi-mj additional columns that replicate normal columns for all modulo mi input lines that are congruent modulo mj. Another modulo mi,j scaling unit includes a barrel shifter-based arithmetic circuit, and a dynamic storage unit coupled to the arithmetic circuit to store the output of the arithmetic circuit.

摘要翻译： 模R加法器和用于RNS的模m，i，j比例缩放单元。 该加法器包括一个模数转换器，以及耦合到桶形移位器以存储桶形移位器的输出的动态存储单元。 在优选实施例中，动态存储单元包括用于桶形移位器的每个输出线的一个动态锁存器，每个动态锁存器包括与逆变器级联的时钟反相器。 一个模数m i，j个缩放单元包括执行残差转换和算术运算两者的修改后的模数移位器。 在不使用组合逻辑的情况下执行残余转换。 在一个优选实施例中，经修改的桶形移位器通过复制正常列的所有模m i / / SUB来执行残余转换 >输入线，它们是等同的模m m。 另一个模数转换单元包括基于桶形移位器的运算电路，以及耦合到运算电路以存储运算电路的输出的动态存储单元。

公开(公告)号：US20060106905A1

公开(公告)日：2006-05-18

申请号：US10990405

申请日：2004-11-17

申请人： William Chren

发明人： William Chren

IPC分类号： G06F1/02

CPC分类号： G06F1/0307 ,  G06F7/4833

摘要： A method for performing addition/subtraction on logarithmic number system (LNS) operands x and y that uses a single lookup table. The lookup table is populated by values of ln(1+exp(−α)) where α is an absolute value of difference of x and y. To perform an addition operation, the lookup table is accessed a single time and the lookup table output added to the largest of the input operands to produce the result. To perform a subtraction operation the addition lookup table is successively addressed by left-shifted versions of α, the table outputs are accumulated, and accumulated lookup table output added to the largest of the input operands to produce the subtraction result.

摘要翻译： 用于使用单个查找表的对数数字系统（LNS）操作数x和y执行加法/减法的方法。 查找表由ln（1 + exp（-alpha））的值填充，其中alpha是x和y的差的绝对值。 为了执行加法运算，查找表被单次访问，​​查找表输出被添加到最大的输入操作数以产生结果。 为了进行减法运算，加法查找表通过左移位版本的alpha连续寻址，表输出被累加，并将积累的查找表输出添加到最大的输入操作数，以产生减法结果。

公开(公告)号：US20060015549A1

公开(公告)日：2006-01-19

申请号：US10889676

申请日：2004-07-13

申请人： William Chren

发明人： William Chren

IPC分类号： G06F7/38

CPC分类号： G06F7/58 ,  G06F7/584

摘要： Samples from a gaussian distribution are used for simulating the performance of communication channels that are corrupted with additive white gaussian noise (AWGN). There is a need for fast, efficient methods of computing these samples, particularly in hardware. Speed of generation is important because, in many cases, the samples must be produced in real-time at the channel data rate. Efficiency of generation is especially important for FPGA-based implementations or other types of design or test systems where on-chip memory is in short supply.

摘要翻译： 来自高斯分布的样本用于模拟通过加性白高斯噪声（AWGN）损坏的通信信道的性能。 需要快速，有效的计算这些样本的方法，特别是在硬件方面。 生成速度很重要，因为在许多情况下，采样必须以通道数据速率实时生成。 生成的效率对于基于FPGA的实现或其他类型的片上存储器不足的设计或测试系统尤其重要。