Method and apparatus for address decoding of embedded DRAM devices
    2.
    发明申请
    Method and apparatus for address decoding of embedded DRAM devices 有权
    嵌入式DRAM器件的地址解码方法和装置

    公开(公告)号:US20050044337A1

    公开(公告)日:2005-02-24

    申请号:US10952269

    申请日:2004-09-28

    IPC分类号: G06F12/00 G06F12/02 G11C8/04

    CPC分类号: G11C8/04

    摘要: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

    摘要翻译: 公开了一种用于解码嵌入式DRAM(eDRAM)设备的存储器阵列地址的方法,该eDRAM器件被配置为与SDRAM存储器管理器一起操作。 在本发明的示例性实施例中,该方法包括在第一时间从存储器管理器接收一组行地址位。 随后,一组初始列地址位在稍后的时间从存储器管理器。 初始列地址位的集合被转换为一组转换的列地址位,并且行地址位集合和转换的列地址位的集合被同时用于访问eDRAM设备中期望的存储器位置。 eDRAM设备中期望的存储器位置具有对应于行地址位集合的值的行地址和对应于转换列地址位集合的值的列地址。