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公开(公告)号：US20100318752A1
公开(公告)日：2010-12-16
申请号：US12485190
申请日：2009-06-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F11/3636
摘要： In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a triggered memory map access (tMMA) system coupled to the at least one core. The tMMA system can receive one or more events and, in response, perform one or more actions. For example, the actions can include transactions which can include a write to a an address of the memory map, a read from an address of the memory map, a read followed by write to two respective addresses of the memory map, and/or a fetch transaction. A result of a transaction (e.g., data read, data written, error, etc.) can be used in generating a trace message. For example, the tMMA system can generate a trace message that includes the result of the transaction and send the trace message to a trace message bus.
摘要翻译： 在一个或多个实施例中，数据处理系统可以包括能够执行指令集架构的指令的至少一个核心以及耦合到所述至少一个核心的触发的存储器映射访问（tMMA）系统。 tMMA系统可以接收一个或多个事件，并作为响应执行一个或多个动作。 例如，动作可以包括可以包括对存储器映射的地址的写入，从存储器映射的地址的读取，随后写入存储器映射的两个相应地址的读取的事务，和/或 提取事务。 事务的结果（例如，数据读取，数据写入，错误等）可用于生成跟踪消息。 例如，tMMA系统可以生成包含事务结果的跟踪消息，并将跟踪消息发送到跟踪消息总线。
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公开(公告)号：US06795942B1
公开(公告)日：2004-09-21
申请号：US09611524
申请日：2000-07-06
申请人： William D. Schwarz
发明人： William D. Schwarz
IPC分类号： G11C2900
CPC分类号： G11C29/72 , G11C29/44 , G11C29/4401
摘要： A method is presented for built-in redundancy analysis of a semiconductor memory device. The method does not require retention of an entire memory bitmap, and may be implemented on-chip and integrated within existing BIST circuitry. The regular memory is comprehensively tested, and defective rows and columns are flagged for replacement by redundant rows and/or columns; the elements containing the most defects are the first to be flagged. If all of the defective memory locations can be replaced using redundant rows and columns, the method designates the memory as repairable; a repair solution may then be scanned out of the memory device. The method is believed to provide a fast, cost-effective means of testing and repairing memory devices, with a consequent improvement in production yields.
摘要翻译： 提出了一种用于半导体存储器件的内置冗余分析的方法。 该方法不需要保留整个存储器位图，并且可以在片上实现并集成在现有的BIST电路中。 常规内存被全面测试，有缺陷的行和列被标记为冗余行和/或列替换; 包含最多缺陷的元素是第一个被标记的元素。 如果可以使用冗余行和列替换所有有缺陷的存储器位置，则该方法将存储器指定为可修复的; 然后可以将修复解决方案从存储设备中扫描出来。 该方法被认为是提供快速，经济有效的测试和修复存储器件的手段，从而提高了生产率。
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3.发明授权Redundancy analysis for embedded memories with built-in self test and built-in self repair 有权嵌入式内存冗余分析，内置自检和内置自我修复
公开(公告)号：US6067262A
公开(公告)日：2000-05-23
申请号：US209938
申请日：1998-12-11
CPC分类号： G11C29/006 , G11C29/12 , G11C2029/0405 , G11C2029/1208 , G11C2029/5604 , G11C2029/5606 , G11C29/72
摘要： An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self-test (BIST) circuitry and built-in-self-repair (BISR) circuitry. A BIST run is then performed on a predetermined portion of the integrated circuit to detect a set of faulty memory locations. The results of this first BIST run are stored. A second condition is applied to the die and a second BIST run is executed to generate a second set of faulty memory locations. The results of the second BIST run are stored and compared with the first result. If the results differ, the integrated circuit is rejected. Thus, a methodology for screening out field errors at the factory is disclosed using BIST/BISR circuitry.
摘要翻译： 一种用于在制造生产测试过程中利用应力因素检测和排除具有嵌入式存储器的故障集成电路的有效方法。 在本发明所公开的实施例中，应力因子被应用于具有内置自测（BIST）电路和内置自修复（BISR）电路的集成电路。 然后在集成电路的预定部分上执行BIST运行以检测一组故障存储器位置。 这个第一个BIST运行的结果被存储。 第二条件被应用于管芯，并且执行第二BIST运行以产生第二组故障存储器位置。 存储第二个BIST运行的结果并将其与第一个结果进行比较。 如果结果不同，则集成电路被拒绝。 因此，使用BIST / BISR电路公开了在工厂筛选场误差的方法。
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公开(公告)号：US08700878B2
公开(公告)日：2014-04-15
申请号：US12485190
申请日：2009-06-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0292 , G06F11/3636
摘要： In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a triggered memory map access (tMMA) system coupled to the at least one core. The tMMA system can receive one or more events and, in response, perform one or more actions. For example, the actions can include transactions which can include a write to a an address of the memory map, a read from an address of the memory map, a read followed by write to two respective addresses of the memory map, and/or a fetch transaction. A result of a transaction (e.g., data read, data written, error, etc.) can be used in generating a trace message. For example, the tMMA system can generate a trace message that includes the result of the transaction and send the trace message to a trace message bus.
摘要翻译： 在一个或多个实施例中，数据处理系统可以包括能够执行指令集架构的指令的至少一个核心以及耦合到所述至少一个核心的触发的存储器映射访问（tMMA）系统。 tMMA系统可以接收一个或多个事件，并作为响应执行一个或多个动作。 例如，动作可以包括可以包括对存储器映射的地址的写入，从存储器映射的地址的读取，随后写入存储器映射的两个相应地址的读取的事务，和/或 提取事务。 事务的结果（例如，数据读取，数据写入，错误等）可用于生成跟踪消息。 例如，tMMA系统可以生成包含事务结果的跟踪消息，并将跟踪消息发送到跟踪消息总线。
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公开(公告)号：US06496947B1
公开(公告)日：2002-12-17
申请号：US09426034
申请日：1999-10-25
申请人： William D. Schwarz
发明人： William D. Schwarz
IPC分类号： G06F1127
CPC分类号： G11C29/12015 , G11C11/41 , G11C29/14 , G11C29/46 , G11C29/50016 , G11C29/70
摘要： A single-chip integrated circuit includes a memory array, a built-in self test circuit and a pause circuit. The built-in self test circuit is coupled to the memory array and is adapted to execute a sequence of write and read operations on the memory array. The pause circuit is coupled to and activated by the built-in self test circuit. When activated, the pause circuit pauses the sequence of write and read operations for a pause time period.
摘要翻译： 单片集成电路包括存储器阵列，内置自检电路和暂停电路。 内置自检电路耦合到存储器阵列，并且适于在存储器阵列上执行写入和读取操作的序列。 暂停电路通过内置自检电路耦合并激活。 当激活时，暂停电路在暂停时间段内暂停写入和读取操作的顺序。
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