公开(公告)号：US07707396B2

公开(公告)日：2010-04-27

申请号：US11561002

申请日：2006-11-17

申请人： Jeffrey P. Bradford ,  Richard W. Doing ,  Richard J. Eickemeyer ,  Wael R. El-Essawy ,  Douglas R. Logan ,  Balaram Sinharoy ,  William E. Speght ,  Lixin Zhang

发明人： Jeffrey P. Bradford ,  Richard W. Doing ,  Richard J. Eickemeyer ,  Wael R. El-Essawy ,  Douglas R. Logan ,  Balaram Sinharoy ,  William E. Speght ,  Lixin Zhang

IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F7/38

CPC分类号： G06F9/3806 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/3017 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3853

摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.

摘要翻译： 处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。 指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。 分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。 分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。 滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。 分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。