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公开(公告)号：US20110161969A1
公开(公告)日：2011-06-30
申请号：US12647417
申请日：2009-12-25
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.
摘要翻译： 计算机系统设置有具有一个或多个处理器核的处理芯片，处理芯片与具有内核空间和用户空间的操作系统通信。 每个处理器核心具有多个核心线程来共享核心资源，每个由操作系统管理的线程用作核心内的独立逻辑处理器。 创建并支持处理器核心的逻辑扩展映射，其中映射包括指示操作系统的使用的每个核心线程，包括用户空间和内核空间以及高速缓存，存储器和非存储器。 提供了一种操作系统调度管理器，用于通过基于线程可用性（如地图中所示）和线程优先级将例程分配给不同的核心线程来调度处理器核心上的例程。
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2.发明申请OPTIMIZING MEMORY ACCESSES FOR MULTI-THREADED PROGRAMS IN A NON-UNIFORM MEMORY ACCESS (NUMA) SYSTEM 审中-公开在非均匀存储器访问（NUMA）系统中优化多线程程序的存储器访问公开(公告)号：US20080196030A1
公开(公告)日：2008-08-14
申请号：US11674278
申请日：2007-02-13
IPC分类号： G06F9/46
CPC分类号： G06F9/5033
摘要： A computer implemented method, apparatus, and computer program product for optimizing a non-uniform memory access system. Each thread in a set of threads is affinitized to a processor in a set of processors at different times to form a temporarily affinitized thread, wherein a single temporarily affinitized thread is present. The set of threads execute on the set of processors to perform one or more tasks each time the temporarily affinitized thread is formed. Information is collected about memory accesses by the temporarily affinitized thread. Based on the collected information about the memory accesses, at least one thread in the set of threads is permanently affinitized to a processor in the set of processors.
摘要翻译： 一种用于优化不均匀存储器访问系统的计算机实现的方法，装置和计算机程序产品。 一组线程中的每个线程在不同时间与一组处理器中的处理器相关联以形成临时关联的线程，其中存在单个临时关联的线程。 该组线程在该组处理器上执行，以在每次形成临时关联的线程时执行一个或多个任务。 收集关于暂时关联的线程的内存访问的信息。 基于收集的关于存储器访问的信息，该组线程中的至少一个线程被永久地附属于处理器集合中的处理器。
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3.发明申请公开(公告)号：US20080104362A1
公开(公告)日：2008-05-01
申请号：US11552652
申请日：2006-10-25
申请人： William M. Buros , Kevin X. Lu , Santhosh Rao , Peter W. Y. Wong
发明人： William M. Buros , Kevin X. Lu , Santhosh Rao , Peter W. Y. Wong
IPC分类号： G06F12/00
CPC分类号： G06F12/1054 , G06F12/0864
摘要： A method, system, and computer program product enable the selective adjustment in the size of memory pages allocated from system memory. In one embodiment, the method includes, but is not limited to, the steps of: collecting profile data (e.g., the number of Translation Lookaside Buffer (TLB) misses, the number of page faults, and the time spent by the Memory Management Unit (MMU) performing page table walks); identifying the top N active processes, where N is an integer that may be user-defined; evaluating the profile data of the top N active processes within a given time period; and in response to a determination that the profile data indicates that a threshold has been exceeded, promoting the pages used by the top N active processes to a larger page size and updating the Page Table Entries (PTEs) accordingly.
摘要翻译： 方法，系统和计算机程序产品使得能够选择性地调整从系统存储器分配的存储器页面的大小。 在一个实施例中，该方法包括但不限于以下步骤：收集简档数据（例如，翻译后备缓冲器（TLB）的次数，页面错误的数量以及存储器管理单元花费的时间 （MMU）执行页表散步）; 识别前N个活动进程，其中N是可以由用户定义的整数; 在给定时间段内评估前N个活动进程的简档数据; 并且响应于所述简档数据指示已经超过阈值的确定，将前N个活动进程使用的页面推广到较大的页面大小并相应地更新页表项（PTE）。
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4.发明授权Logical extended map to demonstrate core activity including L2 and L3 cache hit and miss ratio 有权逻辑扩展映射来演示核心活动，包括L2和L3缓存命中和丢失率公开(公告)号：US09032411B2
公开(公告)日：2015-05-12
申请号：US12647417
申请日：2009-12-25
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.
摘要翻译： 计算机系统设置有具有一个或多个处理器核的处理芯片，处理芯片与具有内核空间和用户空间的操作系统通信。 每个处理器核心具有多个核心线程来共享核心资源，每个由操作系统管理的线程用作核心内的独立逻辑处理器。 创建并支持处理器核心的逻辑扩展映射，其中映射包括指示操作系统的使用的每个核心线程，包括用户空间和内核空间以及高速缓存，存储器和非存储器。 提供了一种操作系统调度管理器，用于通过基于线程可用性（如地图中所示）和线程优先级将例程分配给不同的核心线程来调度处理器核心上的例程。
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