公开(公告)号：US20070155087A1

公开(公告)日：2007-07-05

申请号：US11683439

申请日：2007-03-08

申请人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

发明人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

IPC分类号： H01L21/8238

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/7885

摘要： A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

摘要翻译： 提供了分闸门闪存。 在衬底中形成沟槽以限定活性层。 器件隔离层形成在沟槽中。 器件隔离层的表面低于有源层的表面。 在有源层上形成各自包括隧道电介质层，浮栅和覆盖层的层叠栅极结构。 栅极间电介质层形成在堆叠的栅极结构的侧壁上。 选择栅极形成在层叠的栅极结构的一侧并跨越有源层。 选择栅极电介质层形成在选择栅极和有源层之间。 源极区域形成在堆叠栅极结构的另一侧上的有源层中。 漏极区域形成在选择栅极一侧的有源层中。

公开(公告)号：US07208796B2

公开(公告)日：2007-04-24

申请号：US11163223

申请日：2005-10-11

申请人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

发明人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

摘要翻译： 提供了分闸门闪存。 在衬底中形成沟槽以限定活性层。 器件隔离层形成在沟槽中。 器件隔离层的表面低于有源层的表面。 在有源层上形成各自包括隧道电介质层，浮栅和覆盖层的层叠栅极结构。 栅极间电介质层形成在堆叠的栅极结构的侧壁上。 选择栅极形成在层叠的栅极结构的一侧并跨越有源层。 选择栅极电介质层形成在选择栅极和有源层之间。 源极区域形成在堆叠栅极结构的另一侧上的有源层中。 漏极区域形成在选择栅极一侧的有源层中。

公开(公告)号：US20070048961A1

公开(公告)日：2007-03-01

申请号：US11306897

申请日：2006-01-16

申请人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Yu Lee

发明人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Yu Lee

IPC分类号： H01L21/20

CPC分类号： H01L29/66545 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

摘要： A semiconductor device and fabricating method thereof are provided. In the fabricating method, two trenches are formed in the substrate and, then the first dielectric layers is formed on the sidewalls of the trenches and a source/drain layer is formed in each trench. A second dielectric layer is formed on the substrate and the source/drain layer. Finally, a gate structure is formed on the second dielectric layer. The source/drain layers and the first dielectric layers are placed in trenches; therefore, device dimension can be reduced.

摘要翻译： 提供了一种半导体器件及其制造方法。 在制造方法中，在衬底中形成两个沟槽，然后在沟槽的侧壁上形成第一电介质层，并且在每个沟槽中形成源极/漏极层。 在基板和源极/漏极层上形成第二电介质层。 最后，在第二电介质层上形成栅极结构。 源极/漏极层和第一电介质层被放置在沟槽中; 因此，可以减少设备尺寸。

公开(公告)号：US20060208307A1

公开(公告)日：2006-09-21

申请号：US11163223

申请日：2005-10-11

申请人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

发明人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

摘要翻译： 提供了分闸门闪存。 在衬底中形成沟槽以限定活性层。 器件隔离层形成在沟槽中。 器件隔离层的表面低于有源层的表面。 在有源层上形成各自包括隧道电介质层，浮栅和覆盖层的层叠栅极结构。 栅极间电介质层形成在堆叠的栅极结构的侧壁上。 选择栅极形成在层叠的栅极结构的一侧并跨越有源层。 选择栅极电介质层形成在选择栅极和有源层之间。 源极区域形成在堆叠栅极结构的另一侧上的有源层中。 漏极区域形成在选择栅极一侧的有源层中。