公开(公告)号：US20060250856A1

公开(公告)日：2006-11-09

申请号：US11274967

申请日：2005-11-15

申请人： Claude Bertin ,  Frank Guo ,  Thomas Rueckes ,  Steven Konsek ,  Mitchell Meinhold ,  Max Strasburg ,  Ramesh Sivarajan ,  X. M. Huang

发明人： Claude Bertin ,  Frank Guo ,  Thomas Rueckes ,  Steven Konsek ,  Mitchell Meinhold ,  Max Strasburg ,  Ramesh Sivarajan ,  X. M. Huang

IPC分类号： G11C7/10

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0002 ,  G11C2213/16 ,  G11C2213/19 ,  G11C2213/35 ,  G11C2213/79

摘要： A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell.

公开(公告)号：US20080012047A1

公开(公告)日：2008-01-17

申请号：US11280786

申请日：2005-11-15

申请人： Claude Bertin ,  Mitchell Meinhold ,  Steven Konsek ,  Thomas Ruckes ,  Max Strasburg ,  Frank Guo ,  X. M. Huang ,  Ramesh Sivarajan

发明人： Claude Bertin ,  Mitchell Meinhold ,  Steven Konsek ,  Thomas Ruckes ,  Max Strasburg ,  Frank Guo ,  X. M. Huang ,  Ramesh Sivarajan

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L27/112 ,  B82Y10/00 ,  G11C13/0002 ,  G11C13/025 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/19 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/1052 ,  Y10S977/943

摘要： A two terminal switching device includes first and second conductive terminals and a nanotube article. The article has at least one nanotube, and overlaps at least a portion of each of the first and second terminals. The device also includes a stimulus circuit in electrical communication with at least one of the first and second terminals. The circuit is capable of applying first and second electrical stimuli to at least one of the first and second terminal(s) to change the relative resistance of the device between the first and second terminals between a relatively high resistance and a relatively low resistance. The relatively high resistance between the first and second terminals corresponds to a first state of the device, and the relatively low resistance between the first and second terminals corresponds to a second state of the device.

摘要翻译： 二端开关器件包括第一和第二导电端子和纳米管制品。 该制品具有至少一个纳米管，并且与第一和第二端子中的每一个的至少一部分重叠。 该装置还包括与第一和第二端子中的至少一个电连通的激励电路。 电路能够将第一和第二电刺激施加到第一和第二端子中的至少一个，以在相对较高电阻和相对较低电阻之间改变第一和第二端子之间的器件的相对电阻。 第一和第二端子之间的相对高的电阻对应于器件的第一状态，并且第一和第二端子之间的相对较低的电阻对应于器件的第二状态。

公开(公告)号：US20090052246A1

公开(公告)日：2009-02-26

申请号：US12165007

申请日：2008-06-30

申请人： Claude L. BERTIN ,  Frank GUO ,  Thomas RUECKES ,  Steven L. KONSEK ,  Mitchell MEINHOLD ,  Max STRASBURG ,  Ramesh SIVARAJAN ,  X. M. HUANG

发明人： Claude L. BERTIN ,  Frank GUO ,  Thomas RUECKES ,  Steven L. KONSEK ,  Mitchell MEINHOLD ,  Max STRASBURG ,  Ramesh SIVARAJAN ,  X. M. HUANG

IPC分类号： G11C16/04 ,  G11C11/00 ,  G11C11/50 ,  G11C5/14

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0002 ,  G11C14/0054 ,  G11C2213/19 ,  G11C2213/35 ,  Y10S977/943

摘要： A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.

摘要翻译： 非易失性存储单元包括：易失性存储装置，其响应于电刺激而存储对应的逻辑状态; 以及耦合到所述易失性存储装置的影子存储装置。 影子存储装置响应于电刺激而接收和存储对应的逻辑状态。 影子存储装置包括存储影子装置的相应状态的非易失性纳米管开关。