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    Die casting process incorporating computerized pattern recognition techniques
    4.
    发明授权
    Die casting process incorporating computerized pattern recognition techniques 有权
    包含计算机化模式识别技术的压铸工艺

    公开(公告)号：US08434544B2

    公开(公告)日：2013-05-07

    申请号：US13442628

    申请日：2012-04-09

    Applicant: Arnie Fulton ,  Yan Zhu ,  Michael Bomar

    Inventor： Arnie Fulton ,  Yan Zhu ,  Michael Bomar

    IPC: B22D46/00

    CPC classification number: B22D17/32 ,  B22D46/00

    Abstract: A die casting process using pattern recognition techniques to identify those die castings manufactured under conditions likely to produce a die casting which would subsequently prove unacceptable for use. By promptly identifying such die castings, they may be discarded before being shipped to a remote facility for further processing. As a result, the rejection rate of die castings at the remote facility may be reduced and the raw materials used to form the discarded die castings may be more readily recycled.

    Abstract translation: 使用模式识别技术的压铸方法来识别在可能产生压铸件的条件下制造的那些压铸件，随后将被证明是不可接受的。 通过及时识别这种压铸件，在运送到远程设备进行进一步处理之前，可将其丢弃。 结果，可以减少远程设备的压铸件的排出率，并且用于形成废弃压铸件的原材料可以更容易地再循环。

    Series/parallel connection scheme for energy storage devices
    5.
    发明申请
    Series/parallel connection scheme for energy storage devices 有权

    公开(公告)号：US20130049696A1

    公开(公告)日：2013-02-28

    申请号：US13199440

    申请日：2011-08-29

    Applicant: Li-Yan Zhu ,  Jei Wei Chang ,  Ping Hua Deng

    Inventor： Li-Yan Zhu ,  Jei Wei Chang ,  Ping Hua Deng

    IPC: H02J7/00

    CPC classification number: H02J7/0026 ,  H01M10/4207 ,  H02J7/0029 ,  H02J2007/0039

    Abstract: A battery pack has series-parallel connected battery cells. An inrush current limiting circuit has current limiting devices and a current limiting tracking means limits inrush current from shorted battery cells. Each current limiting tracking means is coupled to the current limiting devices such that they limit an inrush current from parallel neighbor battery cells when one battery cell on the column shorts. The current limiting devices are variable buffer resistors with a positive temperature coefficient. The current limiting tracking means are heat sinks that thermally couples the buffer resistors together such that the buffer resistors increase in resistance with a temperature increase caused by current flowing through the buffer resistor associated with the shorted battery cell. Current regulating elements are in series with columns of battery cells for preventing inrush current to the columns of the battery cells.

    N-bits successive approximation register analog-to-digital converting circuit
    7.
    发明授权
    N-bits successive approximation register analog-to-digital converting circuit 有权
    N位逐次逼近寄存器模数转换电路

    公开(公告)号：US08344931B2

    公开(公告)日：2013-01-01

    申请号：US13150508

    申请日：2011-06-01

    Applicant: Yan Zhu ,  Chi-Hang Chan ,  U-Fat Chio ,  Sai-Weng Sin ,  Seng-Pan U ,  Rui Paulo Da Silva Martins ,  Franco Maloberti

    Inventor： Yan Zhu ,  Chi-Hang Chan ,  U-Fat Chio ,  Sai-Weng Sin ,  Seng-Pan U ,  Rui Paulo Da Silva Martins ,  Franco Maloberti

    IPC: H03M1/12

    CPC classification number: H03M1/002 ,  H03M1/466

    Abstract: The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

    Abstract translation: 本发明提供一种n位逐次逼近寄存器（SAR）模数转换（ADC）电路，包括：n位SAR控制逻辑，包括DACp阵列和采样电容器CSp的p型电容器网络 包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器，其中电源和接地直接连接到p型电容器网络和n型电容器网络，而不使用由p型电容器网络和n型电容器网络产生的参考电压 参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器，n个位寄存器和一个开关逻辑。 比较器包括第一前置放大器，第二前置放大器和动态锁存器。 替代方案，比较器包括四输入前置放大器和动态锁存器。

    Die casting process incorporating computerized pattern recognition techniques
    9.
    发明授权
    Die casting process incorporating computerized pattern recognition techniques 有权
    包含计算机化模式识别技术的压铸工艺

    公开(公告)号：US08167022B2

    公开(公告)日：2012-05-01

    申请号：US13100778

    申请日：2011-05-04

    Applicant: Arnie Fulton ,  Yan Zhu ,  Michael Bomar

    Inventor： Arnie Fulton ,  Yan Zhu ,  Michael Bomar

    IPC: B22D46/00

    CPC classification number: B22D17/32 ,  B22D46/00

    Abstract: A die casting process using pattern recognition techniques to identify those die castings manufactured under conditions likely to produce a die casting which would subsequently prove unacceptable for use. By promptly identifying such die castings, they may be discarded before being shipped to a remote facility for further processing. As a result, the rejection rate of die castings at the remote facility may be reduced and the raw materials used to form the discarded die castings may be more readily recycled.

    Abstract translation: 使用模式识别技术的压铸方法来识别在可能产生压铸件的条件下制造的那些压铸件，随后将被证明是不可接受的。 通过及时识别这种压铸件，在运送到远程设备进行进一步处理之前，可将其丢弃。 结果，可以减少远程设备的压铸件的排出率，并且用于形成废弃压铸件的原材料可以更容易地再循环。

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