公开(公告)号：US08705657B2

公开(公告)日：2014-04-22

申请号：US13159385

申请日：2011-06-13

申请人： Jie-Wei Lai ,  Yang-Chuan Chen

发明人： Jie-Wei Lai ,  Yang-Chuan Chen

IPC分类号： H03C3/00

CPC分类号： H04L27/0008 ,  H04L27/12 ,  H04L27/3427

摘要： A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.

摘要翻译： 数字信号处理电路包括组合级和输出级。 组合级被布置为接收具有相同频率但不同相位的多个不重叠的时钟信号，接收多个第一输入比特流，并且通过根据非接收方式组合第一输入比特流来生成第一输出比特流， - 重叠的时钟信号。 输出级被布置成根据第一输出位流产生输出。 数字信号处理方法包括：接收具有相同频率但不同相位的多个非重叠时钟信号; 接收多个第一输入比特流; 通过根据所述非重叠时钟信号组合所述第一输入比特流来产生第一输出比特流; 以及根据第一输出比特流生成输出。

公开(公告)号：US20120128092A1

公开(公告)日：2012-05-24

申请号：US13159385

申请日：2011-06-13

申请人： Jie-Wei Lai ,  Yang-Chuan Chen

发明人： Jie-Wei Lai ,  Yang-Chuan Chen

IPC分类号： H04L27/00

CPC分类号： H04L27/0008 ,  H04L27/12 ,  H04L27/3427

摘要： A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.

摘要翻译： 数字信号处理电路包括组合级和输出级。 组合级被布置为接收具有相同频率但不同相位的多个不重叠的时钟信号，接收多个第一输入比特流，并且通过根据非接收方式组合第一输入比特流来生成第一输出比特流， - 重叠的时钟信号。 输出级被布置成根据第一输出位流产生输出。 数字信号处理方法包括：接收具有相同频率但不同相位的多个非重叠时钟信号; 接收多个第一输入比特流; 通过根据所述非重叠时钟信号组合所述第一输入比特流来产生第一输出比特流; 以及根据第一输出比特流生成输出。