公开(公告)号：US5231363A

公开(公告)日：1993-07-27

申请号：US924383

申请日：1992-08-03

申请人： Takayuki Sano ,  Yasuhide Igura

发明人： Takayuki Sano ,  Yasuhide Igura

IPC分类号： G06F1/025 ,  G06F7/62

CPC分类号： G06F1/025 ,  G06F7/62

摘要： A pulse width modulating circuit including a shift register and a subtraction circuit, with first and second binary counters respectively connected to the outputs of the shift register and the subtraction circuit, and a logic circuit connected to the outputs of the binary counters. Pulse width control data bits are input to the shift register and the subtraction circuit. The shift register processes the pulse width control data bits by shifting them one bit to the right and dividing the control data bits in half. The output of the shift register is also connected to the subtraction circuit and provides one-half of the pulse width control data bits to the inputs of the subtraction circuit and the first counter. A load signal is respectively applied to the first and second binary counters which are responsive thereto for sensing the left and right edges of a pulse width modulation signal based upon the outputs from the shift register and the subtraction circuit. The pulse width modulation signal is located in the middle of the cycle interval as generated by the load signal. Pulse position correcting circuits may be interposed between the shift register and the first counter, and between the subtraction circuit and the second counter for adjusting the position of the pulse width modulating signal to the middle of the cycle interval.

摘要翻译： 一种包括移位寄存器和减法电路的脉冲宽度调制电路，其中第一和第二二进制计数器分别连接到移位寄存器和减法电路的输出，以及连接到二进制计数器的输出的逻辑电路。 脉冲宽度控制数据位被输入到移位寄存器和减法电路。 移位寄存器通过将它们向右移位一位并将控制数据位分成两半来处理脉冲宽度控制数据位。 移位寄存器的输出也连接到减法电路，并将一半的脉冲宽度控制数据位提供给减法电路和第一个计数器的输入。 负载信号分别施加到对其响应的第一和第二二进制计数器，以基于来自移位寄存器和减法电路的输出来感测脉宽调制信号的左边缘和右边缘。 脉冲宽度调制信号位于由负载信号产生的循环间隔的中间。 脉冲位置校正电路可以插入在移位寄存器和第一计数器之间，以及减法电路和第二计数器之间，用于将脉冲宽度调制信号的位置调整到循环间隔的中间。