公开(公告)号：US10169545B2

公开(公告)日：2019-01-01

申请号：US15097379

申请日：2016-04-13

申请人： Maurice M. Klee

发明人： Maurice M. Klee

IPC分类号： G06F17/50 ,  G06F7/62 ,  G06F19/00 ,  G16H50/50

摘要： Improved computer-implemented tools for use in modeling/simulating spatial charge distributions for electrophysiological systems are provided. The improvements are in three areas: (1) the use of solid angles to calculate quantities of free charge and/or bound charge in calculation cells and/or the movement of quantities of free charge across one or more faces of a calculation cell; (2) the use of flattened calculations cells having only two faces with substantial areas as seen from the free charge and/or the bound charge of the electrophysiological system; and (3) the use of at least two spatial charge distributions, specifically, at least one for bound charge and at least one for free charge, so as to include the effects of relative dielectric constants greater than 1.0 for part or all of an electrophysiological system. The three improvements can be used individually or in combinations.

公开(公告)号：US09092111B2

公开(公告)日：2015-07-28

申请号：US12843863

申请日：2010-07-26

申请人： Patricia Narvaez Cifra ,  Timothy Pressler Clark ,  Gregory Richard Hintermeister ,  Heidi Louise Saufferer

发明人： Patricia Narvaez Cifra ,  Timothy Pressler Clark ,  Gregory Richard Hintermeister ,  Heidi Louise Saufferer

IPC分类号： G06F3/00 ,  G06F3/048 ,  G06F3/0482 ,  G06F9/44 ,  G06F9/45 ,  G06F11/263 ,  G06F11/34 ,  G06F11/36 ,  G06F13/10 ,  G06F13/12 ,  G06F17/00 ,  G06F17/20 ,  G06F17/21 ,  G06F17/22 ,  G06F17/24 ,  G06F17/25 ,  G06F17/26 ,  G06F17/27 ,  G06F17/28 ,  G06F7/62 ,  G06F3/0481 ,  G06F3/0488

CPC分类号： G06F3/04812 ,  G06F3/0481 ,  G06F3/0488 ,  G06F9/451

摘要： Provided are a computer program product, method, and system for capturing information on a rendered user interface including user activatable content. A user interface is executed on the computer system. An initial representation is generated of a rendered user interface. A determination is made of locations rendered in the user interface associated with user activatable content, wherein user activatable content is rendered in response to user selection of a location in the user interface associated with the user activatable content. For each determined location, content is captured from the activatable content rendered in response to the user selecting the determined location to create a captured content object having the captured content. The captured content objects and the initial representation are stored. The initial representation and the captured content objects are processed to generate output to render the initial representation of the user interface and the captured content from the captured content objects.

摘要翻译： 提供了一种用于捕获包括用户可激活内容的渲染用户界面上的信息的计算机程序产品，方法和系统。 在计算机系统上执行用户界面。 生成呈现的用户界面的初始表示。 确定在与用户可激活内容相关联的用户界面中呈现的位置，其中响应于用户对与用户可激活内容相关联的用户界面中的位置的选择来呈现用户可激活内容。 对于每个确定的位置，从响应于用户选择所确定的位置而呈现的可激活内容捕获内容以创建具有所捕获的内容的捕获的内容对象。 捕获的内容对象和初始表示被存储。 处理初始表示和捕获的内容对象以生成输出以从捕获的内容对象呈现用户界面的初始表示和捕获的内容。

公开(公告)号：US08666709B1

公开(公告)日：2014-03-04

申请号：US13611968

申请日：2012-09-12

申请人： William J. Aldrich ,  Gregoire Hamon

发明人： William J. Aldrich ,  Gregoire Hamon

IPC分类号： G06F7/60 ,  G06F17/10 ,  G06F9/455 ,  G06F7/62

CPC分类号： G06F17/5009 ,  G06F8/34 ,  G06F2217/04 ,  G06F2217/74

摘要： A verification tool in a graphical modeling environment allows the components in the graphical modeling environment to be used to define error or exceptional conditions without adverse affects on the ultimate implementation of the model. In one example, a system presents a graphical interface to facilitate design of a model constructed from graphical blocks; receives an association of a plurality of blocks with a verification subsystem; and performs an operation to verify that the blocks in the verification subsystem do not affect operation of the model external to the verification system.

摘要翻译： 图形建模环境中的验证工具允许图形建模环境中的组件用于定义错误或特殊条件，而不会对模型的最终实现产生不利影响。 在一个示例中，系统呈现图形界面以便于由图形块构建的模型的设计; 接收多个块与验证子系统的关联; 并且执行操作以验证验证子系统中的块不影响验证系统外部的模型的操作。

公开(公告)号：US08347123B2

公开(公告)日：2013-01-01

申请号：US12632797

申请日：2009-12-08

申请人： Richard Thomas Schultz

发明人： Richard Thomas Schultz

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F7/38 ,  G06F7/62 ,  G06F17/50 ,  H03B21/00 ,  H03K5/01 ,  G04F1/00 ,  G01R25/00

CPC分类号： H03K3/012

摘要： Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation.

公开(公告)号：US07460988B2

公开(公告)日：2008-12-02

申请号：US10404002

申请日：2003-03-31

申请人： Shinsaku Higashi

发明人： Shinsaku Higashi

IPC分类号： G06F17/50 ,  G06F7/62 ,  G06F9/45 ,  G06F9/455 ,  H03K17/693

CPC分类号： G01R31/318307 ,  G01R31/318342 ,  G01R31/31907

摘要： There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of the test signal generating timings output by the timing alignment section to generate the test signal in simulation in the cycle time corresponding to the test signal generating timing.

摘要翻译： 提供了一种用于模拟测试装置的测试仿真器，该测试装置包括用于将测试信号分别提供给被测试器件的多个测试模块，包括：多个测试模块仿真部分，用于仿真基于不同的测试信号生成测试信号的多个测试模块 循环，用于仿真用于控制被测设备的测试的控制装置的控制仿真部分，用于产生测试信号产生定时的同步仿真部分，多个测试模块仿真部分中的每个测试信号产生定时部分将在其中生成测试信号 基于来自控制仿真部分的指令，对应于测试模块仿真部分的周期时间的模拟定时对准部分，用于对准由同步仿真部分按时间顺序产生的多个测试信号产生定时，并且通过 一个以及用于引起测试模块仿真部分的调度部分 对应于由定时对准部分输出的测试信号产生定时之一，以在对应于测试信号产生定时的周期时间中在仿真中产生测试信号。

公开(公告)号：US20080154390A1

公开(公告)日：2008-06-26

申请号：US11645134

申请日：2006-12-22

申请人： Zhi Zhou ,  Jing Ou ,  Donald F. Rohr ,  Vishnu Poonamallee

发明人： Zhi Zhou ,  Jing Ou ,  Donald F. Rohr ,  Vishnu Poonamallee

IPC分类号： G05B13/04 ,  G06F7/62 ,  H01M8/04

CPC分类号： H01M8/0612 ,  H01M8/04089 ,  H01M8/04223 ,  H01M8/04225 ,  H01M8/04228 ,  H01M8/04302 ,  H01M8/04303 ,  H01M8/04305 ,  Y02P70/56

摘要： A technique includes providing a mathematical model of reactant production by a reactant processor of a fuel cell system. The technique also includes during a time period in which the fuel cell system is continuously operating, adapting the model based on feedback received from the fuel cell system and controlling the fuel cell system using an indication of the reactant production from the model.

摘要翻译： 一种技术包括提供由燃料电池系统的反应物处理器产生的反应物的数学模型。 该技术还包括在燃料电池系统连续运行的时间段期间，基于从燃料电池系统接收的反馈来适应模型，并且使用来自模型的反应物产生的指示来控制燃料电池系统。

公开(公告)号：US07376939B1

公开(公告)日：2008-05-20

申请号：US10072212

申请日：2002-02-07

申请人： Anshuman Nayak ,  Malay Haldar ,  Alok Choudhary ,  Vikram Saxena ,  Prithviraj Banerjee

发明人： Anshuman Nayak ,  Malay Haldar ,  Alok Choudhary ,  Vikram Saxena ,  Prithviraj Banerjee

IPC分类号： G06F9/45 ,  G06F9/455 ,  G06F17/50 ,  G06F7/62 ,  G06F9/44

CPC分类号： G06F17/5045 ,  G06F17/5031

摘要： Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. Further, techniques are provided for modeling the timing behavior of a function or functional block without drawing a timing diagram; understanding the interface behavior of a function block which captures the timing waveforms; specifying virtual functions which are built using basic functional units and their timing behavior; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.

摘要翻译： 电子设计自动化工具规定了系统级及其组件（包括嵌入式处理器，算术逻辑单元（ALU），乘法器，分频器，嵌入式存储器元件，可编程逻辑单元等）的知识产权（IP）内核的架构。 指定IP内核及其接口; 并通过其界面了解IP内核和功能。 此外，提供了用于对功能或功能块的定时行为建模而不绘制时序图的技术; 了解捕获时序波形的功能块的接口行为; 指定使用基本功能单元构建的虚拟功能及其时序行为; 解析和创建用于分析编译规范的内部图形表单; 匹配架构规范中的组件及其实例化以映射从应用程序生成的输入图中的计算; 并将规范映射到目标的组件上。

公开(公告)号：US07313509B2

公开(公告)日：2007-12-25

申请号：US10345338

申请日：2003-01-16

申请人： Megumi Nagata ,  Masaki Tosaka

发明人： Megumi Nagata ,  Masaki Tosaka

IPC分类号： G06F7/62

CPC分类号： G06F17/5036

摘要： A simulation method makes a noise analysis based on parameters including a conductor resistance which takes skin effect into consideration. The simulation method calculates a first resistance of one of conductors having a largest cross sectional area, obtains a predetermined pitch which saturates a diagonal component of a second resistance of a conductor with reference to the first resistance and makes the diagonal component approximately constant, by varying a pitch of the conductors, calculates the parameters for each pitch with respect to one of the pitches larger than or equal to the predetermined pitch and the pitches smaller than the predetermined pitch, and substitutes the parameters calculated for the one of the pitches with respect to the other of the pitches, and outputs calculation results.

摘要翻译： 仿真方法基于参数考虑皮肤效应的导体电阻进行噪声分析。 仿真方法计算具有最大横截面面积的一个导体的第一电阻，获得相对于第一电阻使导体的第二电阻的对角线分量饱和的预定间距，并使对角分量近似恒定，通过改变 导体的间距，相对于大于或等于预定间距的间距和间距小于预定间距的一个间距计算每个间距的参数，并且将针对一个间距计算的参数代替相对于 另一个音调，并输出计算结果。

公开(公告)号：US07031895B1

公开(公告)日：2006-04-18

申请号：US09572937

申请日：2000-05-18

申请人： Eiichi Takahashi ,  Ken Yokoyama ,  Naohiro Tamura

发明人： Eiichi Takahashi ,  Ken Yokoyama ,  Naohiro Tamura

IPC分类号： G06F17/50 ,  G06F7/62 ,  G06F15/173

CPC分类号： H04L41/147 ,  G06F17/5009 ,  G06F2217/04 ,  H04L41/0853 ,  H04L41/145

摘要： Upon receipt of an end point list, a model setting unit requests the measurement/information collection unit to search a path. The model setting unit receives a path appliance list from the measurement/information collection unit, and generates the configuration of a simulation model of a network. The model setting unit selects an appropriate model for each component of the configuration of the simulation model. Then, the model setting unit sets the parameter value of the model based on the measurement result and the collected information received from the measurement/information collection unit, and automatically generates the simulation model of the network.

摘要翻译： 在接收到终点列表时，模型设置单元请求测量/信息收集单元搜索路径。 模型设置单元从测量/信息收集单元接收路径装置列表，并且生成网络的仿真模型的配置。 模型设置单元为仿真模型配置的每个组件选择适当的模型。 然后，模型设定单元基于测量结果和从测量/信息收集单元接收的收集信息来设定模型的参数值，并自动生成网络的仿真模型。

公开(公告)号：US07003746B2

公开(公告)日：2006-02-21

申请号：US10686022

申请日：2003-10-14

申请人： Stanley M. Hyduke ,  Slawomir Grabowski

发明人： Stanley M. Hyduke ,  Slawomir Grabowski

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F7/62 ,  G06F9/455

CPC分类号： G06F17/5027

摘要： A method and system for accelerating software simulator operation with the aid of reprogrammable hardware such as Field Programmable Gate Array devices (FPGA). The method and system aid in emulation and prototyping of Application Specific Integrated Circuits (ASIC) digital circuit designs by means of reprogrammable devices. The system includes a design verification manager and software program that includes subroutines of finding clock sources, finding synchronous primitives that are receiving clock signals from the clock sources, and a subroutine for inserting edge detector circuits between such clock sources and synchronous primitives. This new method allows eliminating of clock timing issues by applying basic design clocks to the clock enable instead of clock trigger inputs and generating and applying to clock trigger inputs a new clock that is automatically delayed in respect to all other clocks in the design. This system solves the major obstacle for automatic retargeting of ASIC designs into reprogrammable devices that have different timings of the clocking chains in ASICs and FPGAs that result in triggering of associated flip-flops and latches at different times.

摘要翻译： 借助于现场可编程门阵列器件（FPGA）等可编程硬件来加速软件仿真器运行的方法和系统。 该方法和系统通过可重复编程的设备来辅助应用专用集成电路（ASIC）数字电路设计的仿真和原型设计。 该系统包括设计验证管理器和软件程序，其包括查找时钟源的子程序，发现从时钟源接收时钟信号的同步原语，以及用于在这样的时钟源和同步原语之间插入边缘检测器电路的子程序。 这种新方法允许通过将基本设计时钟应用于时钟使能而不是时钟触发输入来消除时钟定时问题，并产生并向时钟触发输入应用相对于设计中所有其他时钟自动延迟的新时钟。 该系统解决了将ASIC设计自动重新定位到可编程器件中的主要障碍，这些器件具有ASIC和FPGA中时钟链的不同时序，导致在不同时间触发相关的触发器和锁存器。