专利检索 ap:"Ye-Sin RYU" 第 1 页

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发明申请
MEMORY MODULES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS 审中-公开

公开(公告)号：US20180152206A1

公开(公告)日：2018-05-31

申请号：US15664295

申请日：2017-07-31

申请人： Hoon SIN , Sang-Uhn CHA , Ye-Sin RYU , Seong-Jin CHO

发明人： Hoon SIN , Sang-Uhn CHA , Ye-Sin RYU , Seong-Jin CHO

IPC分类号： H03M13/29 , G06F11/10

CPC分类号： H03M13/2906 , G06F11/1048 , G06F11/1076 , H03M13/09 , H03M13/13

摘要： A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.