公开(公告)号：US07190286B2

公开(公告)日：2007-03-13

申请号：US11314236

申请日：2005-12-22

Applicant: Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I. Ismail

Inventor： Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I. Ismail

IPC: H03M7/46 ,  H03M7/00

CPC classification number: G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

Abstract translation: 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。

公开(公告)号：US06992603B2

公开(公告)日：2006-01-31

申请号：US10813084

申请日：2004-03-31

Applicant: Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I Ismail

Inventor： Maged M. Ghoneima ,  Peter Caputa ,  Muhammad M. Khellah ,  Ram Krishnamurthy ,  James W. Tschanz ,  Yiben Ye ,  Vivek K. De ,  Yehea I Ismail

IPC: H03M7/00

CPC classification number: G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

Abstract translation: 提供互连架构以降低功耗。 第一驱动器可以在第一互连上驱动信号，并且第二驱动器可以在第二互连上驱动信号。 第一驱动器可以由第一电压供电，并且第二驱动器可以由不同于第一电压的第二电压供电。

公开(公告)号：US06789237B1

公开(公告)日：2004-09-07

申请号：US10142276

申请日：2002-05-09

Applicant: Yehea I. Ismail

Inventor： Yehea I. Ismail

IPC: G06F1750

CPC classification number: G06F17/504

Abstract: A method for mapping moments in a reduced order system of approximation order q for use in simulating a circuit or system having n state variables at n nodes, the circuit or system having I inputs. The method includes calculating only q+I moments, where q is the approximation order and I is the number of inputs of the circuit or system being simulated, sorting the state variables at the n nodes, selecting q nodes of the n nodes, and calculating the dominate poles and zeros using a multi-point moment matching algorithm to simultaneously match q+I moments at the selected q nodes of the circuit or system. In one embodiment, the method includes using extra dummy inputs such that the total number of inputs equals I, such that K*I>q where K is a constant having a value in the range of about 4 to 8.

Abstract translation: 用于在逼近阶数q的简化系统中映射矩的方法，用于模拟在n个节点处具有n个状态变量的电路或系统，该电路或系统具有I个输入。 该方法包括仅计算q + I矩，其中q是近似次数，I是正在仿真的电路或系统的输入数，对n个节点进行状态变量的排序，选择n个节点的q个节点，并计算 使用多点时刻匹配算法的主导极和零，以同时匹配电路或系统的所选q个节点处的q + I时刻。 在一个实施例中，该方法包括使用额外的虚拟输入，使得输入的总数等于I，使得K * I> q其中K是具有在大约4至8的范围内的值的常数。