公开(公告)号：US4796224A

公开(公告)日：1989-01-03

申请号：US15349

申请日：1987-02-17

申请人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Yoshikazu Maeyama

发明人： Hideki Kawai ,  Masaru Fujii ,  Kiyoto Ohta ,  Yoshikazu Maeyama

IPC分类号： G11C7/00 ,  G11C5/02 ,  G11C11/401 ,  G11C11/41

CPC分类号： G11C5/025

摘要： In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of the control signal lines and data lines can be minimized so that the stray or parasitic capacitance is reduced, and a higher speed and stable operation of the device is thereby realized.

摘要翻译： 在半导体存储装置中，将存储单元阵列分离为基板上的至少两个部分，并且诸如移位寄存器的串行存储元件和控制信号线共同设置在两个存储单元阵列部分之间，并且由 通过这种布置，可以使控制信号线和数据线的长度最小化，从而减小杂散或寄生电容，从而实现装置的更高的速度和稳定的操作。

公开(公告)号：US5233557A

公开(公告)日：1993-08-03

申请号：US723613

申请日：1991-07-01

申请人： Masahiko Sakagami ,  Yoshikazu Maeyama

发明人： Masahiko Sakagami ,  Yoshikazu Maeyama

IPC分类号： G11C11/413 ,  G06F1/06 ,  G11C7/22

CPC分类号： G11C7/22

摘要： A memory control device for controlling a random access memory provides with an arbiter for generating write start and read start signals in response to WRITE and READ commands which are obtained by frequency-dividing writing and reading clock signals, respectively and a memory control circuit comprised of first and second delay circuits for delaying the write start and read start signals by predetermined times, respectively, and first and second RS flip-flop circuits for generating write and read control signals in response to the write start and read start signals, respectively, which are reset by reset signals output from the first and second delay circuits, respectively.