公开(公告)号：US07126950B2

公开(公告)日：2006-10-24

申请号：US09782879

申请日：2001-02-13

申请人： Kazuo Takagi ,  Naoya Henmi ,  Shinobu Sasaki ,  Kurenai Murakami ,  Motoo Nishihara ,  Yoshinori Rokugou

发明人： Kazuo Takagi ,  Naoya Henmi ,  Shinobu Sasaki ,  Kurenai Murakami ,  Motoo Nishihara ,  Yoshinori Rokugou

IPC分类号： H04L12/28 ,  H03M13/00

CPC分类号： H04L1/0061 ,  H04L1/0072 ,  H04L1/0079 ,  H04L1/0085

摘要： A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.

摘要翻译： 存储电路定义用于存储第一数据单元的第一有效载荷信号的第一标题位的第一字段，用于存储第一有效载荷信号的第二字段和第三字段。 第一标题位在第二数据单元的第二有效载荷信号的数量与第二标题位相等。 分割电路将第一标题位除以生成多项式以产生第一错误校验码。 使用相同的生成多项式来分割第二标题位以产生第二错误校验码。 通过生成多项式将假设标题位的余数除以第一错误校验码，以产生插入存储电路的第二字段的和。 假设的头部位数量大于第一和第二场域中总位数，从而第一和第二数据单元可以通过第一和第二数据单元的不同错误检查结果彼此区分开。

公开(公告)号：US20060193325A1

公开(公告)日：2006-08-31

申请号：US11414415

申请日：2006-05-01

申请人： Kazuo Takagi ,  Naoya Henmi ,  Shinobu Sasaki ,  Kurenai Murakami ,  Motoo Nishihara ,  Yoshinori Rokugou

发明人： Kazuo Takagi ,  Naoya Henmi ,  Shinobu Sasaki ,  Kurenai Murakami ,  Motoo Nishihara ,  Yoshinori Rokugou

IPC分类号： H04L12/28

CPC分类号： H04L1/0061 ,  H04L1/0072 ,  H04L1/0079 ,  H04L1/0085

摘要： A storage circuit defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit divides the first header bits by a generator polynomial to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.