公开(公告)号：US08621415B2

公开(公告)日：2013-12-31

申请号：US13372434

申请日：2012-02-13

申请人： Kenta Suto ,  Satoshi Shibatani ,  Ryoji Ishikawa ,  Ken Saito ,  Yoshio Inoue

发明人： Kenta Suto ,  Satoshi Shibatani ,  Ryoji Ishikawa ,  Ken Saito ,  Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5068 ,  G06F2217/78 ,  G06F2217/84

摘要： A power domain is automatically generated.A computer performs a function simulation process 9 for evaluating whether or not a designed circuit satisfies a specification, and a clustering process 10 which obtains a power domain by clustering logical blocks in which activation timings are within a range, based on the result of the function simulation process. Since the power domain is obtained by a process performed by the computer, the power domain can be optimized compared to a case when it is obtained by hand (manual work of the designer).

摘要翻译： 电源域自动生成。 计算机执行功能模拟处理9，用于评估设计的电路是否满足规格;以及聚类处理10，其基于功能的结果，通过对激活定时在一定范围内的逻辑块进行聚类而获得功率域 模拟过程。 由于通过计算机执行的处理获得功率域，所以与通过手动（设计人员的手工工作）获得的情况相比，能够优化功率域。

公开(公告)号：US08423931B2

公开(公告)日：2013-04-16

申请号：US12785480

申请日：2010-05-23

申请人： Aya Sakurai ,  Yoshio Inoue

发明人： Aya Sakurai ,  Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A computer-readable recording medium stores a design support program causing a computer to perform: detecting a data path and a clock path corresponding to the data path making up a partial circuit in a circuit-under-design; selecting an object cell from cells on the data path and the clock path detected in the detecting; replacing the object cell selected in the selecting with a cell having a function substantially identical to and characteristics different from the object cell; acquiring a plurality of types of characteristic information related to the partial circuit based on the data path and the clock path after the object cell is replaced in the replacing; determining whether the types of the characteristic information acquired in the acquiring is in violation of restrictions; and outputting a determination result determined in the determining.

摘要翻译： 计算机可读记录介质存储使计算机执行以下操作的设计支持程序：检测在构成电路设计之外的构成部分电路的数据路径的数据路径和时钟路径; 从数据路径上的小区和在检测中检测到的时钟路径选择对象单元; 用具有与目标单元基本相同的特征的单元替换在选择中选择的对象单元; 在所述替换中替换所述对象单元之后，基于所述数据路径和所述时钟路径获取与所述部分电路相关的多种类型的特征信息; 确定在获取中获取的特征信息的类型是否违反限制; 并输出在确定中确定的确定结果。

公开(公告)号：US08108809B2

公开(公告)日：2012-01-31

申请号：US12219371

申请日：2008-07-21

申请人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

发明人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.

摘要翻译： 本发明涉及一种从网表上对集成电路进行路由分析的路由分析方法，网表是构成集成电路的多个小区的信息和连接小区的路由，路由分析方法包括步骤（步骤1 ），将要定义为常数C的多个单元的区域的数量，单元的数量或将单元从网表连接的路线的数量进行计算，并计算作为正方形的面积的布局区域S 布局区域，通过将常数C除以预定的常数U，通过将具有步骤1中获得的布局区域S的布局区域的半周长H乘以预定的步骤（步骤2）来计算总路线长度L的步骤（步骤2） 系数α，以及通过将总路由长度L除以布局区域S来计算路由难度指标的步骤（步骤3）。因此，本发明提供了一种用于集成的路由分析方法 其中，允许以高精度的预测计算路由难度指数。

公开(公告)号：US20120005641A1

公开(公告)日：2012-01-05

申请号：US13166349

申请日：2011-06-22

申请人： Masanori KURIMOTO ,  Takashi Tsukamoto ,  Yoshio Inoue

发明人： Masanori KURIMOTO ,  Takashi Tsukamoto ,  Yoshio Inoue

IPC分类号： G06F9/455

CPC分类号： G06F17/505 ,  G06F2217/78 ,  G06F2217/84

摘要： The present invention provides a semiconductor designing apparatus realizing dispersed power consumption timings without causing a setup violation and a hold violation. An STA unit calculates a setup slack as a margin of setup time of a flip-flop on the basis of a present design value of a clock latency of the flip-flop. Based on the calculated setup slack, an HSLD unit adjusts the clock latency of the flip-flop so as to be advanced more than a present design value without causing a timing violation. When a peak equal to or larger than a threshold value remains in the number of synchs in a clock latency distribution as a result of the latency control of the HSLD unit, a PAS unit smoothes the clock latency of the flip-flop without causing a timing violation on the basis of the timing information recalculated by the HSLD unit.

摘要翻译： 本发明提供一种实现分散的功耗定时的半导体设计装置，而不会造成设置违规和保持违规。 STA单元基于触发器的时钟延迟的当前设计值来计算作为触发器的建立时间的余量的建立松弛。 基于计算出的设置松弛，HSLD单元调整触发器的时钟延迟，以便超过当前设计值而不会导致定时违规。 当等于或大于阈值的峰值作为HSLD单元的等待时间控制的结果在时钟延迟分布中保持同步的数量时，PAS单元平滑触发器的时钟延迟而不引起定时 基于由HSLD单元重新计算的定时信息的违规。

公开(公告)号：US07835888B2

公开(公告)日：2010-11-16

申请号：US11389009

申请日：2006-03-27

申请人： Yoshio Inoue ,  Takashi Yoneda ,  Masaru Ito

发明人： Yoshio Inoue ,  Takashi Yoneda ,  Masaru Ito

IPC分类号： G06F17/10

CPC分类号： G06F17/5081 ,  G06F17/5036

摘要： A method for efficiently extracting a variation distribution of a characteristic for a semiconductor integrated circuit. The method extracts a characteristic distribution of a semiconductor integrated circuit by performing a mathematical analysis using a polynomial expression based on a variation distribution of a process sensitivity parameter.

摘要翻译： 一种用于有效提取半导体集成电路的特性的变化分布的方法。 该方法通过使用基于处理灵敏度参数的变化分布的多项式表达式进行数学分析来提取半导体集成电路的特性分布。

公开(公告)号：US20080295055A1

公开(公告)日：2008-11-27

申请号：US12219371

申请日：2008-07-21

申请人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

发明人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.

摘要翻译： 本发明涉及一种从网表上对集成电路进行路由分析的路由分析方法，网表是构成集成电路的多个小区的信息和连接小区的路由，路由分析方法包括步骤（步骤1 ），将要定义为常数C的多个单元的区域的数量，单元的数量或将单元从网表连接的路线的数量进行计算，并计算作为正方形的面积的布局区域S 布局区域，通过将常数C除以预定的常数U，通过将具有步骤1中获得的布局区域S的布局区域的半周长H乘以预定的步骤（步骤2）来计算总路线长度L的步骤（步骤2） 系数α，以及通过将总路由长度L除以布局区域S来计算路由难度指标的步骤（步骤3）。因此，本发明提供了一种用于int的路由分析方法 集成电路，允许以高精度的预测计算路由难度指标。

公开(公告)号：US20070184301A1

公开(公告)日：2007-08-09

申请号：US10590158

申请日：2005-02-16

申请人： Tomohiro Oshiyama ,  Hiroshi Kita ,  Yoshio Inoue ,  Shuichi Oi

发明人： Tomohiro Oshiyama ,  Hiroshi Kita ,  Yoshio Inoue ,  Shuichi Oi

IPC分类号： H01L51/54 ,  C09K11/06

CPC分类号： H01L51/0087 ,  C07F15/0086 ,  C09K11/06 ,  C09K2211/1029 ,  C09K2211/185 ,  H01L51/004 ,  H01L51/0054 ,  H01L51/006 ,  H01L51/0068 ,  H01L51/007 ,  H01L51/0071 ,  H01L51/008 ,  H01L51/0081 ,  H01L51/5016 ,  H05B33/14 ,  Y10S428/917

摘要： A material for an organic electroluminescence element, characterized in that it comprises a platinum complex formed from a platinum ion and a ligand having at least one aryl group being not capable of free rotation or at least one aromatic heterocyclic group being not capable of free rotation; a display device, characterized in that it comprises said material for an organic electroluminescence element and exhibits high luminous efficiency and long luminous life; and an illumination device, characterized in that it comprises said material for an organic electroluminescence element and exhibits high luminous efficiency and long luminous life.

摘要翻译： 一种有机电致发光元件的材料，其特征在于，其包含由铂离子形成的铂络合物和具有至少一个芳基不能自由旋转的配体或至少一个不能自由旋转的芳族杂环基团; 一种显示装置，其特征在于，其包括用于有机电致发光元件的所述材料，并且具有高发光效率和长的发光寿命; 以及照明装置，其特征在于，其包含所述有机电致发光元件用材料，发光效率高，发光寿命长。

公开(公告)号：US20070130552A1

公开(公告)日：2007-06-07

申请号：US11362926

申请日：2006-02-28

申请人： Yoshio Inoue

发明人： Yoshio Inoue

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A required value of decoupling capacitance is calculated in advance for every functional cell, a virtual cell which has a functional cell, and a decoupling capacitance placing area required for placing the decoupling capacitance with the calculated value is created, the virtual cell is placed on a chip, and the decoupling capacitance cell is subsequently placed in the decoupling capacitance placing area of the virtual cell. A layout method of an integrated circuit and a computer program, in which a decoupling capacitance with an amount required for preventing malfunction caused by a noise can be surely placed, and there is no possibility that the functional cell will need to be replaced due to a shortage of the decoupling capacitance after placing the functional cell can be realized.

摘要翻译： 对于每个功能单元预先计算去耦电容的所需值，产生具有功能单元的虚拟单元和将去耦电容放置在计算值所需的去耦电容放置面积上，将虚拟单元放置在 芯片，并且去耦电容单元随后被放置在虚拟单元的去耦电容放置区域中。 集成电路和计算机程序的布局方法可以可靠地放置具有防止由噪声引起的故障所需的量的去耦电容，并且不可能由于功能单元而需要更换功能单元 可以实现放置功能单元之后的去耦电容的不足。

公开(公告)号：US20070106966A1

公开(公告)日：2007-05-10

申请号：US11389009

申请日：2006-03-27

申请人： Yoshio Inoue ,  Takashi Yoneda ,  Masaru Ito

发明人： Yoshio Inoue ,  Takashi Yoneda ,  Masaru Ito

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036

摘要： A method for efficiently extracting a variation distribution of a characteristic for a semiconductor integrated circuit. The method extracts a characteristic distribution of a semiconductor integrated circuit by performing a mathematical analysis using a polynomial expression based on a variation distribution of a process sensitivity parameter.

摘要翻译： 一种用于有效提取半导体集成电路的特性的变化分布的方法。 该方法通过使用基于处理灵敏度参数的变化分布的多项式表达式进行数学分析来提取半导体集成电路的特性分布。

公开(公告)号：US20050246676A1

公开(公告)日：2005-11-03

申请号：US11111720

申请日：2005-04-22

申请人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

发明人： Toshiyuki Sadakane ,  Ken Saito ,  Yoshio Inoue

IPC分类号： G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5077

摘要： The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.

摘要翻译： 本发明涉及一种从网表上对集成电路进行路由分析的路由分析方法，网表是构成集成电路的多个小区的信息和连接小区的路由，路由分析方法包括步骤（步骤1 ），将要定义为常数C的多个单元的区域的数量，单元的数量或将单元从网表连接的路线的数量进行计算，并计算作为正方形的面积的布局区域S 布局区域，通过将常数C除以预定的常数U，通过将具有步骤1中获得的布局区域S的布局区域的半周长H乘以预定的步骤（步骤2）来计算总路线长度L的步骤（步骤2） 系数α，以及通过将总路由长度L除以布局区域S来计算路由难度指标的步骤（步骤3）。因此，本发明提供了一种用于 集成电路，允许以高精度的预测计算路由难度指标。