公开(公告)号：US4717942A

公开(公告)日：1988-01-05

申请号：US635538

申请日：1984-07-30

申请人： Kunio Nakamura ,  Yukinori Kuroki

发明人： Kunio Nakamura ,  Yukinori Kuroki

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10861 ,  H01L27/10829

摘要： A semiconductor memory cell of a single field effect transistor and a single capacitor is surrounded or delimited at its three sides in the plan view by grooves formed in a semiconductor substrate. The capacitor in each memory cell is formed on one side wall surface or both side wall surfaces of this groove. With such construction, an increase in a capacitance can be achieved and a degree of circuit integration can be enhanced in distinction from the case where a groove is provided within an active region, that is, within a plan region of a capacitor section.

摘要翻译： 单个场效应晶体管和单个电容器的半导体存储单元在平面图中由其形成在半导体衬底中的沟槽的三侧围绕或界定。 每个存储单元中的电容器形成在该凹槽的一个侧壁表面或两个侧壁表面上。 通过这样的结构，与电容器部的平面区域内的有源区域内设置沟槽的情况相比，可以实现电容的增加，并且可以提高电路集成度。