公开(公告)号：US20190042329A1

公开(公告)日：2019-02-07

申请号：US16024563

申请日：2018-06-29

Applicant: Utkarsh Y. Kakaiya ,  Pratik Marolia ,  Joshua David Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur ,  Yuling Yang ,  David Alexander Munday

Inventor： Utkarsh Y. Kakaiya ,  Pratik Marolia ,  Joshua David Fender ,  Sundar Nadathur ,  Nagabhushan Chitlur ,  Yuling Yang ,  David Alexander Munday

IPC: G06F9/50 ,  G06F13/42

Abstract: A system is provided that includes a host processor coupled to a programmable acceleration coprocessor. The coprocessor may include logic for implementing a physical function and multiple associated virtual functions. The coprocessor may include a static programmable resource interface circuit (PIC) configured to perform management functions and one or more partial reconfiguration regions, each of which can be loaded with an accelerator function unit (AFU). An AFU may further be partitioned into AFU contexts (AFCs), each of which can be mapped to one of the virtual functions. The PIC enables hardware discovery/enumeration and loading of device drivers such that security isolation and interface performance are maintained.