公开(公告)号：US06660612B1

公开(公告)日：2003-12-09

申请号：US10289606

申请日：2002-11-07

申请人： Yung Shan Chang ,  Theodore S. Moise, IV ,  Scott R. Summerfelt

发明人： Yung Shan Chang ,  Theodore S. Moise, IV ,  Scott R. Summerfelt

IPC分类号： H01L2176

CPC分类号： H01L27/11502 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/11507 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： One aspect of the invention relates to a method of manufacturing a semiconductor device in which an alignment mark is formed by a plurality of adjacent filled trenches. A processing tool detects the trenches as though they were a single filled trench of larger dimension. When the trenches are metal filled, the metal is more easily protected from oxidation than when the metal is formed into a single large trench, an effect that is pronounced when the trenches are filled with tungsten. Another aspect of the invention relates to an alignment mark formed by a plurality of tungsten filled trenches. The alignment mark can be used to align the pattern for an FeRAM capacitor stack to underlying tungsten contacts.

摘要翻译： 本发明的一个方面涉及一种半导体器件的制造方法，其中通过多个相邻的填充沟槽形成对准标记。 处理工具检测沟槽，好像它们是较大尺寸的单个填充沟槽。 当沟槽被金属填充时，与当金属形成单个大沟槽时相比，金属更容易被保护以免氧化，这是当沟槽被钨填充时的效果。 本发明的另一方面涉及由多个填充钨的沟槽形成的对准标记。 对准标记可用于将FeRAM电容器堆叠的图案对准下层钨触点。

公开(公告)号：US20060284173A1

公开(公告)日：2006-12-21

申请号：US11155149

申请日：2005-06-17

申请人： Manuel Quevedo-Lopez ,  Yung-Shan Chang

发明人： Manuel Quevedo-Lopez ,  Yung-Shan Chang

IPC分类号： H01L23/58 ,  H01L29/10

CPC分类号： H01L21/76224 ,  H01L22/12 ,  H01L22/20

摘要： A shallow trench isolation (STI) test pattern comprising a plurality of test structures. Each of the test structures comprise at least two lines comprising a predefined line length, line width, and gap between the lines. At least one of the line length, line width and gap are different between each of the plurality of the test structures.

摘要翻译： 包括多个测试结构的浅沟槽隔离（STI）测试图案。 每个测试结构包括至少两条线，其包括预定线长度，线宽和线之间的间隙。 多个测试结构中的每一个之间的线长，线宽和间隙中的至少一个是不同的。