公开(公告)号：US09659928B2

公开(公告)日：2017-05-23

申请号：US14644243

申请日：2015-03-11

申请人： Advanced Micro Devices, Inc.

发明人： Andy Wei ,  Roman Boschke ,  Markus Forsberg

IPC分类号： H01L29/49 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L27/088 ,  H01L21/76224 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823842 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/4238 ,  H01L2924/0002 ,  Y10S438/959 ,  Y10S438/975 ,  H01L2924/00

摘要： By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.

公开(公告)号：US09347879B2

公开(公告)日：2016-05-24

申请号：US14873120

申请日：2015-10-01

申请人： KLA-Tencor Corporation

发明人： Michael Adel ,  Walter D. Mieher ,  Mark Ghinovker

IPC分类号： H01L23/58 ,  G01N21/47 ,  G01N21/95

CPC分类号： G01B11/272 ,  G01N21/4785 ,  G01N21/9501 ,  G03F7/70633 ,  H01L21/68 ,  H01L21/682 ,  H01L23/544 ,  Y10S438/975

摘要： Disclosed is a scatterometry mark for determining an overlay error, critical dimension, or profile of the mark. The mark includes a first plurality of periodic structures on a first layer, a second plurality of periodic structures on a second layer, and a third plurality of periodic structures on a third layer that is underneath the first and second layer. The third periodic structures are perpendicular to the first and second structures, and the third periodic structures have one or more characteristics so as to result in a plurality of lower structures beneath the third periodic structures being screened from significantly affecting at least part of a spectrum of a plurality of scattered signals detected from the first and second periodic structures for determining an overlay error, critical dimension, or profile of the first and second periodic structures or at least one of such detected scattered signals.

摘要翻译： 公开了用于确定标记的重叠误差，临界尺寸或轮廓的散射测量标记。 标记包括第一层上的第一多个周期性结构，第二层上的第二多个周期性结构以及位于第一和第二层下面的第三层上的第三多个周期性结构。 第三周期性结构垂直于第一和第二结构，并且第三周期结构具有一个或多个特性，以便导致第三周期结构下方的多个下部结构被屏蔽，从而显着影响至少部分频谱 从第一和第二周期结构检测的多个散射信号，用于确定第一和第二周期结构的重叠误差，临界尺寸或轮廓，或这些检测到的散射信号中的至少一个。

公开(公告)号：US09105675B2

公开(公告)日：2015-08-11

申请号：US13874777

申请日：2013-05-01

申请人： Nikon Corporation

发明人： Kazuya Okamoto

IPC分类号： H01L21/00 ,  H01L21/68 ,  H01L21/67 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L21/68 ,  H01L21/67253 ,  H01L21/67259 ,  H01L25/0657 ,  H01L25/50 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

摘要翻译： 堆叠装置，其堆叠各自具有与电路图案和电极连续布置的多个芯片的芯片组件，包括：允许任意移动的多个级，其上放置芯片组件; 存储单元，其存储在堆叠处理期间当放置在所述多个级上的所述芯片组件施加热量时期望发生的每个芯片处的电极的位置的估计变化范围; 以及控制单元，其基于从所述存储单元提供的每个芯片处的所述电极的所述位置的估计的变化范围和所述位置信息，所述控制单元在所述堆叠处理期间设定要相对于彼此假设的所述多个级的位置， 在芯片组件处形成的单个芯片并且控制多个级中的至少一个级。

公开(公告)号：US08921136B2

公开(公告)日：2014-12-30

申请号：US13743523

申请日：2013-01-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Neng-Kuo Chen ,  Shao-Ming Yu ,  Gin-Chen Huang ,  Chia-Jung Hsu ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC分类号： H01L21/66 ,  H01L21/302 ,  H01L21/461 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/00 ,  H01L23/29 ,  H01L29/76 ,  H01L29/66 ,  H01L27/088 ,  H01L29/788 ,  H01L21/02 ,  H01L29/78

CPC分类号： H01L23/528 ,  H01L21/02167 ,  H01L21/76897 ,  H01L23/53257 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

摘要翻译： 本公开涉及形成自对准接触的方法和相关装置。 在一些实施例中，该方法形成了散布在多个介质线之间的多条栅极线，其中栅极线和介质线在有效区域上沿第一方向延伸。 多条栅极线中的一条或多条是沿着第一方向排列的多个栅极线部分。 多个介质线中的一个或多个被切割成沿第一方向排列的多个介质线段。 虚设隔离材料沿第一方向沉积在相邻介质部分之间并且在第一方向上沉积在相邻的栅线部分之间。 然后通过用接触金属代替有效区域上的多个介质线中的一个或多个的一部分来形成一个或多个自对准的金属接触。

公开(公告)号：US08841784B2

公开(公告)日：2014-09-23

申请号：US13553579

申请日：2012-07-19

申请人： Masahiro Ishida

发明人： Masahiro Ishida

IPC分类号： H01L23/544 ,  H01L23/00

CPC分类号： H01L23/562 ,  H01L23/544 ,  H01L23/564 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall.

摘要翻译： 半导体装置包括具有主表面的半导体衬底，形成在半导体衬底的主表面上的多层结构电路，形成在与多层结构电路的最上层相同的层中以围绕多层结构的保护壁 平面图中的电路，以及与最上层形成在同一层中的对准标记。 对准标记形成为与保护壁的至少一部分接触。

公开(公告)号：US08835276B2

公开(公告)日：2014-09-16

申请号：US12964141

申请日：2010-12-09

申请人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Nobuhiro Tsuji ,  Toshiyuki Morishita

发明人： Syouji Nogami ,  Tomonori Yamaoka ,  Shoichi Yamauchi ,  Nobuhiro Tsuji ,  Toshiyuki Morishita

IPC分类号： H01L21/76 ,  H01L23/544 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L21/30604 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/308 ,  H01L23/544 ,  H01L29/0634 ,  H01L29/66712 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A semiconductor substrate is provided in which an alignment mark is formed that can be used for an alignment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. A trench is formed in an alignment region of an N+-type substrate. This trench is used to leave voids after the formation of an N−-type layer. Then, the voids formed in the N+-type substrate can be used as an alignment mark. Thus, such a semiconductor substrate can be used to provide an alignment in the subsequent step of manufacturing the semiconductor apparatus. Thus, the respective components constituting the semiconductor apparatus can be formed at desired positions accurately.

摘要翻译： 提供了一种半导体衬底，其中形成了即使在通过外延膜的平坦化形成杂质扩散层之后也可以用于取向的对准标记。 在N +型衬底的取向区域中形成沟槽。 这种沟槽用于在形成N型层之后留下空隙。 然后，可以使用形成在N +型衬底中的空隙作为对准标记。 因此，可以使用这样的半导体衬底在制造半导体器件的后续步骤中提供对准。 因此，能够精确地形成构成半导体装置的各个部件。

公开(公告)号：US20140197499A1

公开(公告)日：2014-07-17

申请号：US13743523

申请日：2013-01-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Neng-Kuo Chen ,  Shao-Ming Yu ,  Gin-Chen Huang ,  Chia-Jung Hsu ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC分类号： H01L21/02 ,  H01L29/78

CPC分类号： H01L23/528 ,  H01L21/02167 ,  H01L21/76897 ,  H01L23/53257 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

摘要翻译： 本公开涉及形成自对准接触的方法和相关装置。 在一些实施例中，该方法形成了散布在多个介质线之间的多条栅极线，其中栅极线和介质线在有效区域上沿第一方向延伸。 多条栅极线中的一条或多条是沿着第一方向排列的多个栅极线部分。 多个介质线中的一个或多个被切割成沿第一方向排列的多个介质线段。 虚设隔离材料沿第一方向沉积在相邻介质部分之间并且在第一方向上沉积在相邻的栅线部分之间。 然后通过用接触金属代替有效区域上的多个介质线中的一个或多个的一部分来形成一个或多个自对准的金属接触。

公开(公告)号：US08463419B2

公开(公告)日：2013-06-11

申请号：US12617380

申请日：2009-11-12

申请人： Wen-Yao Hsieh ,  Che-Yu Chiu ,  Anwei Peng ,  Jian-Hung Chen ,  Hsueh-Chen Wu

发明人： Wen-Yao Hsieh ,  Che-Yu Chiu ,  Anwei Peng ,  Jian-Hung Chen ,  Hsueh-Chen Wu

IPC分类号： G06F19/00

CPC分类号： G05B19/02 ,  G03F7/70458 ,  G05B19/402 ,  G05B19/41885 ,  G05B2219/45031 ,  Y02P90/20 ,  Y02P90/26 ,  Y10S438/975

摘要： System and method for automated semiconductor manufacturing is provided. In accordance with one aspect of the present invention, a system for automated semiconductor wafer manufacturing includes a smart overlay control (SOC) database having empirical alignment data related to overlay alignment, and a simulation module communicatively coupled to the SOC database, the simulation module determining a simulated overlay alignment of a wafer on the plurality of photolithography tools in a tool bank based on the empirical alignment data stored in the SOC database. The system also includes a dispatch module communicatively coupled to the SOC database and the simulation module, the dispatch module controlling the dispatch of a wafer to one of a plurality of photolithography tools in a tool bank based at least in part on the simulated overlay alignment.

摘要翻译： 提供了自动半导体制造的系统和方法。 根据本发明的一个方面，一种用于自动半导体晶片制造的系统包括具有与重叠对准相关的经验对准数据的智能覆盖控制（SOC）数据库，以及通信地耦合到SOC数据库的仿真模块，模拟模块确定 基于存储在SOC数据库中的经验对准数据，在工具库中的多个光刻工具上的晶片的模拟覆盖对准。 该系统还包括通信地耦合到SOC数据库和模拟模块的调度模块，该调度模块至少部分地基于模拟的重叠对齐来控制将晶片分配到工具库中的多个光刻工具中的一个。

公开(公告)号：US20130105976A1

公开(公告)日：2013-05-02

申请号：US13725695

申请日：2012-12-21

申请人： Micron Technology, Inc.

发明人： Gurtej S. Sandhu ,  Randal W. Chance ,  William T. Rericha

IPC分类号： H01L23/50

CPC分类号： H01L23/50 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/1052 ,  H01L27/10894 ,  H01L2924/0002 ,  Y10S438/95 ,  Y10S438/975 ,  H01L2924/00

摘要： Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction. In the other direction, use of photolithography and a shadowing effect caused by the relative heights of the photoresist and the narrow mask lines causes the wider mask lines to be formed with a rounded corner, thus increasing alignment tolerances in that direction by increasing the distance to a neighboring narrow mask line.

摘要翻译： 在集成电路的阵列区域中用于形成互连的窄掩模线之间的对准公差和用于在集成电路的外围形成互连的较宽的掩模线增加。 通过间距倍增形成窄屏蔽线，通过光刻法形成较宽的掩模线。 较宽的掩模线对准，使得这些线的一侧与窄线的相应侧齐平或嵌入。 较宽的掩模线的相对侧突出超过窄掩模线的对应的相对侧。 较宽的掩模线形成在具有小于窄掩模线的高度的高度的负光致抗蚀剂中。 有利地，窄掩模线可以防止掩模线在一个方向上的膨胀，从而增加该方向上的对准公差。 在另一个方向上，使用光刻法和由光致抗蚀剂和窄掩模线的相对高度引起的阴影效应导致较宽的掩模线形成有圆角，从而通过增加到该方向的距离来增加该方向上的对准公差 相邻的窄屏线。

公开(公告)号：US08420434B2

公开(公告)日：2013-04-16

申请号：US13064175

申请日：2011-03-09

申请人： Yuichi Yamamoto ,  Hayato Iwamoto

发明人： Yuichi Yamamoto ,  Hayato Iwamoto

IPC分类号： H01L21/00

CPC分类号： H01L27/14627 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14601 ,  H01L27/14625 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.