SYSTEM AND METHOD FOR VERIFYING PCB LAYOUT
    1.
    发明申请
    SYSTEM AND METHOD FOR VERIFYING PCB LAYOUT 失效
    用于验证PCB布局的系统和方法

    公开(公告)号:US20120185819A1

    公开(公告)日:2012-07-19

    申请号:US13244625

    申请日:2011-09-25

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5077

    摘要: In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.

    摘要翻译: 在使用计算装置验证印刷电路板(PCB)布局的方法中,从计算装置的存储装置获得PCB模拟文件,并且根据PCB仿真文件在显示装置上显示PCB图像。 PCB图像包括多个信号线和开关电压调节器节点(SVRN)。 从PCB图像中选择要检查的SVRN,并搜索SVRN周围的所有信号线。 该方法计算所选择的SVRN与所搜索的信号线之间的布局距离,并且生成图形窗口界面以定位其布局距离等于或小于最小距离的信号线。 该方法通过将布局距离增加到最小距离来进一步修改定位信号线的布局以满足布局设计规范。

    System and method for verifying PCB layout
    2.
    发明授权
    System and method for verifying PCB layout 失效
    验证PCB布局的系统和方法

    公开(公告)号:US08402423B2

    公开(公告)日:2013-03-19

    申请号:US13244625

    申请日:2011-09-25

    IPC分类号: G06F17/50 G06F9/455

    CPC分类号: G06F17/5077

    摘要: In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.

    摘要翻译: 在使用计算装置验证印刷电路板(PCB)布局的方法中,从计算装置的存储装置获得PCB模拟文件,并且根据PCB仿真文件在显示装置上显示PCB图像。 PCB图像包括多个信号线和开关电压调节器节点(SVRN)。 从PCB图像中选择要检查的SVRN,并搜索SVRN周围的所有信号线。 该方法计算所选择的SVRN与所搜索的信号线之间的布局距离,并且生成图形窗口界面以定位其布局距离等于或小于最小距离的信号线。 该方法通过将布局距离增加到最小距离来进一步修改定位信号线的布局以满足布局设计规范。