公开(公告)号：US20160246827A1

公开(公告)日：2016-08-25

申请号：US15026561

申请日：2013-11-28

Applicant: Gang DENG ,  Xi TANG ,  Zhongyan LU ,  Tao ZHANG ,  Heyuan LIU ,  INTEL CORPORATION

Inventor： Gang Deng ,  Xi Tang ,  Zhongyan Lu ,  Ting Lou ,  Tao Zhong ,  Heyuan Liu

IPC: G06F17/30 ,  G06F12/08

CPC classification number: G06F17/30324 ,  G06F12/0884 ,  G06F17/30138 ,  G06F17/30486 ,  G06F2212/22

Abstract: Techniques for block-based indexing are described. In one embodiment, for example, an apparatus may comprise a multicore processor element, an assignment component for execution by the multicore processor element to generate a plurality of block-attribute pairs, each block-attribute pair corresponding to an attribute value and one of a plurality of data blocks, and an indexing component for execution by the multicore processor element to generate an index block for the plurality of data blocks based on the plurality of block-attribute pairs, the indexing component to perform parallel indexing of the plurality of block-attribute pairs using multiple indexing instances. Other embodiments are described and claimed.

Abstract translation: 描述了基于块的索引的技术。 在一个实施例中，例如，设备可以包括多核处理器元件，用于由多核处理器元件执行以产生多个块属性对的分配组件，每个对应于属性值的块属性对，以及一个 多个数据块，以及索引部件，用于由多核处理器元件执行以基于多个块属性对为多个数据块生成索引块，所述索引组件执行多个块属性对的并行索引， 使用多个索引实例的属性对。 描述和要求保护其他实施例。

公开(公告)号：US20210064531A1

公开(公告)日：2021-03-04

申请号：US17092803

申请日：2020-11-09

Applicant: Francesc Guim Bernat ,  Karthik Kumar ,  Alexander Bachmutsky ,  Zhongyan Lu ,  Thomas Willhalm

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Alexander Bachmutsky ,  Zhongyan Lu ,  Thomas Willhalm

IPC: G06F12/0817

Abstract: Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory. In connection with DM cache operations, such as cache lines evicted from a CPU, logic implemented in hardware determines whether a cache line in a DM cache is to be convicted and implements the software-defined caching policy for the DM cache including associated memory coherency operations.