公开(公告)号：US11095218B2

公开(公告)日：2021-08-17

申请号：US16255342

申请日：2019-01-23

Applicant: ABOV SEMICONDUCTOR CO., LTD.

Inventor： Hong Jin Kim ,  Suk Kyun Hong ,  Hyun Kyu Kim ,  Eung Oh ,  Suk Yun

IPC: H02M3/158 ,  H02M1/38 ,  H02M1/00 ,  H02M1/088

Abstract: A low-power direct current-direct current (DC-DC) converter includes a capacitor, an inductor electrically connected to the capacitor, a first switch configured to be turned on for a first switching interval and supply energy from an input power source to the inductor for the first switching interval, a second switch configured to be turned on for a second switching interval and electrically connect the inductor and a ground terminal for the second switching interval, and a switching control circuit configured to generate first and second switching signals. The switching control circuit is further configured to generate a first sample signal by sampling the voltage level of a first node, and to determine, responding to the first sample signal in time domain, an pulse width adjustment adapted to adjust at least one of the length of a second switching interval and the length of a common blocking interval.

公开(公告)号：US20190229607A1

公开(公告)日：2019-07-25

申请号：US16255342

申请日：2019-01-23

Applicant: ABOV SEMICONDUCTOR CO., LTD.

Inventor： Hong Jin Kim ,  Suk Kyun Hong ,  Hyun Kyu Kim ,  Eung Oh ,  Suk Yun

IPC: H02M1/088 ,  H02M3/158

Abstract: A low-power direct current-direct current (DC-DC) converter includes a capacitor, an inductor electrically connected to the capacitor, a first switch configured to be turned on for a first switching interval and supply energy from an input power source to the inductor for the first switching interval, a second switch configured to be turned on for a second switching interval and electrically connect the inductor and a ground terminal for the second switching interval, and a switching control circuit configured to generate first and second switching signals. The switching control circuit is further configured to generate a first sample signal by sampling the voltage level of a first node, and to determine, responding to the first sample signal in time domain, an pulse width adjustment adapted to adjust at least one of the length of a second switching interval and the length of a common blocking interval.