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公开(公告)号:US10732979B2
公开(公告)日:2020-08-04
申请号:US16011010
申请日:2018-06-18
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Marius Evers , Aparna Thyagarajan , Ashok T. Venkatachar
Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.
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公开(公告)号:US11599359B2
公开(公告)日:2023-03-07
申请号:US16877112
申请日:2020-05-18
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Arun A. Nair , Ashok T. Venkatachar , Emil Talpes , Srikanth Arekapudi , Rajesh Kumar Arunachalam
Abstract: A processor in a data processing system includes a master-shadow physical register file and a renaming unit. The master-shadow physical register file has a master storage coupled to shadow storage. The renaming unit is coupled to the master-shadow physical register file. Based on an occurrence of shadow transfer activation conditions verified by the renaming unit, data in the master storage is transferred from the master storage to the shadow storage for storage. Data is transferred from the shadow storage back to the master storage based on the occurrence of a shadow-to-master transfer event, which includes, for example, a flush of the master storage by the processor.
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公开(公告)号:US12204908B2
公开(公告)日:2025-01-21
申请号:US15997344
申请日:2018-06-04
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Marius Evers , Douglas Williams , Ashok T. Venkatachar , Sudherssen Kalaiselvan
Abstract: A branch predictor predicts a first outcome of a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. Information representing a remainder of the first block is stored in response to the first predicted outcome being taken. In response to the first branch instruction being not taken, the branch predictor is restarted based on the remainder block. In some cases, entries corresponding to second blocks along speculative paths from the first block are accessed using an address of the first block as an index into a branch prediction structure. Outcomes of branch instructions in the second blocks are concurrently predicted using a corresponding set of instances of branch conditional logic and the predicted outcomes are used in combination with the remainder block to restart the branch predictor in response to mispredictions.
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公开(公告)号:US11416256B2
公开(公告)日:2022-08-16
申请号:US16945275
申请日:2020-07-31
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Marius Evers , Aparna Thyagarajan , Ashok T. Venkatachar
Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.
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