公开(公告)号：US20210149819A1

公开(公告)日：2021-05-20

申请号：US17135325

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jagadish B. KOTRA ,  Gabriel H. LOH ,  Matthew R. POREMBA

IPC: G06F12/1045 ,  G09C1/00

Abstract: A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system or encrypts the cache lines to protect against vulnerabilities.