公开(公告)号：US20190163632A1

公开(公告)日：2019-05-30

申请号：US15825880

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. WALKER ,  Michael W. BOYER ,  Yasuko ECKERT ,  Gabriel H. LOH

IPC: G06F12/0817 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811

Abstract: A method includes monitoring, at a cache coherence directory, states of cachelines stored in a cache hierarchy of a data processing system using a plurality of entries of the cache coherence directory. Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.

公开(公告)号：US20200065246A1

公开(公告)日：2020-02-27

申请号：US16108696

申请日：2018-08-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael W. BOYER ,  Gabriel H. LOH ,  Yasuko ECKERT ,  William L. WALKER

IPC: G06F12/0817 ,  G06F12/0842 ,  G06F11/30

Abstract: A processor partitions a coherency directory into different regions for different processor cores and manages the number of entries allocated to each region based at least in part on monitored recall costs indicating expected resource costs for reallocating entries. Examples of monitored recall costs include a number of cache evictions associated with entry reallocation, the hit rate of each region of the coherency directory, and the like, or a combination thereof. By managing the entries allocated to each region based on the monitored recall costs, the processor ensures that processor cores associated with denser memory access patterns (that is, memory access patterns that more frequently access cache lines associated with the same memory pages) are assigned more entries of the coherency directory.