公开(公告)号：US20250110875A1

公开(公告)日：2025-04-03

申请号：US18374757

申请日：2023-09-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Srikanth Reddy Gruddanti ,  Krishnaiah Gummidipudi ,  Prasant Kumar Vallur ,  David Hugh McIntyre ,  Ramon Apostol Mangaser

IPC: G06F12/0811

Abstract: An accelerated processor includes a processor core die including a plurality of compute units, the plurality of compute units including a first level (L1) cache. The accelerated processor also includes a plurality of memory cache dies coupled to the processor core die, the plurality of memory cache dies including a last level cache (LLC) such as a level 3 (L3) cache. The accelerated processor includes an LLC controller to issue a cache access request to the LLC and, based on a latency of the cache access request, direct the cache access request to a subset of the plurality of memory cache dies.