公开(公告)号：US20220083233A1

公开(公告)日：2022-03-17

申请号：US17497286

申请日：2021-10-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Seyed Mohammad SEYEDZADEHDELCHEH ,  Xianwei ZHANG ,  Bradford BECKMANN ,  Shomit N. DAS

IPC: G06F3/06 ,  G06F12/0875

Abstract: In some embodiments, a memory controller in a processor includes a base value cache, a compressor, and a metadata cache. The compressor is coupled to the base value cache and the metadata cache. The compressor compresses a data block using at least a base value and delta values. The compressor determines whether the size of the data block exceeds a data block threshold value. Based on the determination of whether the size of the compressed data block generated by the compressor exceeds the data block threshold value, the memory controller transfers only a set of the compressed delta values to memory for storage. A decompressor located in the lower level cache of the processor decompresses the compressed data block using the base value stored in the base value cache, metadata stored in the metadata cache and the delta values stored in memory.