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公开(公告)号:US20220083119A1
公开(公告)日:2022-03-17
申请号:US17533548
申请日:2021-11-23
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Vedula Venkata Srikant BHARADWAJ
IPC: G06F1/3225 , G06F1/3296 , G06F1/324
Abstract: A processing unit includes compute units partitioned into one or islands that are provided with operating voltages and clock signals having clock frequencies independent of providing operating voltages or clock signals to other islands of compute units. The processing unit also includes dynamic voltage and frequency scaling (DVFS) hardware configured to compute one or more numbers of active memory barriers in the one or more islands. The DVFS hardware is also configured to modify the operating voltages or clock frequencies provided to the one or more islands in response to a change in numbers of active memory barriers in the one or more islands. In some cases, the operating voltage or clock frequency provided to an island is increased in response to the number of active memory barriers in the island decreasing. The operating voltage or clock frequency provided to the island is decreased in response to the number of active memory barriers in the island increasing.
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公开(公告)号:US20220197524A1
公开(公告)日:2022-06-23
申请号:US17128844
申请日:2020-12-21
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Max RUTTENBERG , Vedula Venkata Srikant BHARADWAJ , Yasuko ECKERT , Mark H. OSKIN , Anthony GUTIERREZ
IPC: G06F3/06
Abstract: A processor sets memory timing parameters based on a profile of a workload to be executed at the processor and based on a thermal budget associated with the processor. For a given workload and amount of available thermal headroom, as indicated by a detected temperature, the processor adjusts one or more of the memory timing parameters according to the workload profile. The processor is thereby able to tailor the memory timing parameters according to the memory access behavior of the workload, improving overall processing efficiency.
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公开(公告)号:US20200379543A1
公开(公告)日:2020-12-03
申请号:US16425414
申请日:2019-05-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Vedula Venkata Srikant BHARADWAJ
IPC: G06F1/3225 , G06F1/324 , G06F1/3296
Abstract: A processing unit includes compute units partitioned into one or islands that are provided with operating voltages and clock signals having clock frequencies independent of providing operating voltages or clock signals to other islands of compute units. The processing unit also includes dynamic voltage and frequency scaling (DVFS) hardware configured to compute one or more numbers of active memory barriers in the one or more islands. The DVFS hardware is also configured to modify the operating voltages or clock frequencies provided to the one or more islands in response to a change in numbers of active memory barriers in the one or more islands. In some cases, the operating voltage or clock frequency provided to an island is increased in response to the number of active memory barriers in the island decreasing. The operating voltage or clock frequency provided to the island is decreased in response to the number of active memory barriers in the island increasing.
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