MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE
    1.
    发明申请
    MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE 审中-公开
    用于计算设备的多级地址翻译

    公开(公告)号:US20150095610A1

    公开(公告)日:2015-04-02

    申请号:US14101948

    申请日:2013-12-10

    Inventor: Amos Ben-Meir

    Abstract: Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual address to physical address translations and intermediate physical address to physical address translations in the shared TLB, logic configured to receive a virtual address for translation from a requester, logic configured to conduct a table walk of a translation table in the shared TLB to determine a translated physical address in accordance with the virtual address, and logic configured to transmit the translated physical address to the requester.

    Abstract translation: 本文公开了在虚拟化系统环境中提供地址转换。 作为示例,提供了一种存储器管理装置,其包括共享翻译后备缓冲器(TLB),其包括多个翻译类型,每个翻译类型支持多个页面大小,一个或多个处理器和配置的存储器管理控制器 与一个或多个处理器一起工作。 存储器管理控制器包括配置用于将虚拟地址缓存到物理地址转换和中间物理地址到共享TLB中的物理地址转换的逻辑,被配置为从请求者接收用于转换的虚拟地址的逻辑,被配置为执行 在共享TLB中的转换表,以根据虚拟地址确定翻译的物理地址,以及配置为将转换的物理地址传送到请求者的逻辑。

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