公开(公告)号：US20230325464A1

公开(公告)日：2023-10-12

申请号：US18133302

申请日：2023-04-11

Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY

Inventor： Erfan Bank Tavakoli ,  Fengbo Ren ,  Michael Riera ,  Masudul Quraishi

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: A high-performance computing (HPC) framework for accelerating sparse Cholesky factorization on field-programmable gate arrays (FPGAs) is provided. The proposed framework includes an FPGA kernel implementing a throughput-optimized hardware architecture for accelerating a supernodal multifrontal algorithm for sparse Cholesky factorization. The proposed framework further includes a host program implementing a novel scheduling algorithm for finding the optimal execution order of supernode computations for an elimination tree on the FPGA to eliminate the need for off-chip memory access for storing intermediate results. Moreover, the proposed scheduling algorithm minimizes on-chip memory requirements for buffering intermediate results by resolving the dependency of parent nodes in an elimination tree through temporal parallelism.