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Patent Agency Ranking
公开(公告)号：US11777520B2
公开(公告)日：2023-10-03
申请号：US17218738
申请日：2021-03-31
Inventor： Zhikang Zhang , Fengbo Ren , Kai Xu
CPC classification number: H03M7/6047 , G06N3/045 , G06N3/08 , G06N3/084 , G06N20/20
Abstract: A compression ratio (CR) adapter (CRA) for end-to-end data-driven compressive sensing (CS) reconstruction (EDCSR) frameworks is provided. EDCSR frameworks achieve state-of-the-art reconstruction performance in terms of reconstruction speed and accuracy for images and other signals. However, existing EDCSR frameworks cannot adapt to a variable CR. For applications that desire a variable CR, existing EDCSR frameworks must be trained from scratch at each CR, which is computationally costly and time-consuming. Embodiments described herein present a CRA framework that addresses the variable CR problem generally for existing and future EDCSR frameworks with no modification to given reconstruction models nor enormous additional rounds of training needed. The CRA exploits an initial reconstruction network to generate an initial estimate of reconstruction results based on a small portion of acquired image measurements. Subsequently, the CRA approximates full measurements for the main reconstruction network by complementing the sensed measurements with a re-sensed initial estimate.
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公开(公告)号：US11468542B2
公开(公告)日：2022-10-11
申请号：US16745817
申请日：2020-01-17
Inventor： Fengbo Ren , Kai Xu , Zhikang Zhang
Abstract: This disclosure addresses the single-image compressive sensing (CS) and reconstruction problem. A scalable Laplacian pyramid reconstructive adversarial network (LAPRAN) facilitates high-fidelity, flexible and fast CS image reconstruction. LAPRAN progressively reconstructs an image following the concept of the Laplacian pyramid through multiple stages of reconstructive adversarial networks (RANs). At each pyramid level, CS measurements are fused with a contextual latent vector to generate a high-frequency image residual. Consequently, LAPRAN can produce hierarchies of reconstructed images and each with an incremental resolution and improved quality. The scalable pyramid structure of LAPRAN enables high-fidelity CS reconstruction with a flexible resolution that is adaptive to a wide range of compression ratios (CRs), which is infeasible with existing methods.
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公开(公告)号：US12211173B2
公开(公告)日：2025-01-28
申请号：US18045740
申请日：2022-10-11
Inventor： Fengbo Ren , Kai Xu , Zhikang Zhang
IPC: G06T3/4046 , G06N3/045 , G06N3/084 , G06N20/20 , G06T5/50
Abstract: This disclosure addresses the single-image compressive sensing (CS) and reconstruction problem. A scalable Laplacian pyramid reconstructive adversarial network (LAPRAN) facilitates high-fidelity, flexible and fast CS image reconstruction. LAPRAN progressively reconstructs an image following the concept of the Laplacian pyramid through multiple stages of reconstructive adversarial networks (RANs). At each pyramid level, CS measurements are fused with a contextual latent vector to generate a high-frequency image residual. Consequently, LAPRAN can produce hierarchies of reconstructed images and each with an incremental resolution and improved quality. The scalable pyramid structure of LAPRAN enables high-fidelity CS reconstruction with a flexible resolution that is adaptive to a wide range of compression ratios (CRs), which is infeasible with existing methods.
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公开(公告)号：US20230325464A1
公开(公告)日：2023-10-12
申请号：US18133302
申请日：2023-04-11
Inventor： Erfan Bank Tavakoli , Fengbo Ren , Michael Riera , Masudul Quraishi
IPC: G06F17/16
CPC classification number: G06F17/16
Abstract: A high-performance computing (HPC) framework for accelerating sparse Cholesky factorization on field-programmable gate arrays (FPGAs) is provided. The proposed framework includes an FPGA kernel implementing a throughput-optimized hardware architecture for accelerating a supernodal multifrontal algorithm for sparse Cholesky factorization. The proposed framework further includes a host program implementing a novel scheduling algorithm for finding the optimal execution order of supernode computations for an elimination tree on the FPGA to eliminate the need for off-chip memory access for storing intermediate results. Moreover, the proposed scheduling algorithm minimizes on-chip memory requirements for buffering intermediate results by resolving the dependency of parent nodes in an elimination tree through temporal parallelism.
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公开(公告)号：US11763165B2
公开(公告)日：2023-09-19
申请号：US17317372
申请日：2021-05-11
Inventor： Zhikang Zhang , Fengbo Ren
IPC: G06N3/084 , G06F16/901 , G06N3/04 , G06N3/08 , G06F18/213 , G06V10/764 , G06V10/82
CPC classification number: G06N3/084 , G06F16/901 , G06F18/213 , G06N3/04 , G06N3/08 , G06V10/764 , G06V10/82
Abstract: A data-driven nonuniform subsampling approach for computation-free on-sensor data dimensionality is provided, referred to herein as selective sensing. Designing an on-sensor data dimensionality reduction scheme for efficient signal sensing has long been a challenging task. Compressive sensing is a generic solution for sensing signals in a compressed format. Although compressive sensing can be directly implemented in the analog domain for specific types of signals, many application scenarios require implementation of data compression in the digital domain. However, the computational complexity involved in digital-domain compressive sensing limits its practical application, especially in resource-constrained sensor devices or high-data-rate sensor devices. Embodiments described herein provide a selective sensing framework that adopts a novel concept of data-driven nonuniform subsampling to reduce the dimensionality of acquired signals while retaining the information of interest in a computation-free fashion.
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