公开(公告)号：US20160350115A1

公开(公告)日：2016-12-01

申请号：US15091674

申请日：2016-04-06

Applicant: ARM LIMITED

Inventor： Albin Pierrick TONNERRE ,  Luca SCALABRINO ,  Adam Raymond DULEY

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384

Abstract: An apparatus has decoding circuitry to decode instructions to generate micro-operations, and register rename circuitry to map architectural register specifiers specified by the instructions to physical registers to be accessed in response to the micro-operations. In response to an instruction specifying a selected architectural register specifier as both a source register and a destination register, for which the decoding circuitry is to generate two or more micro-operations, the register rename circuitry stores an indication of a physical register previously mapped to said selected architectural register specifier. In response to one of the micro-operations for which the source register corresponds to the selected architectural register specifier and which follows a micro-operation for which the destination register corresponds to the selected architectural register specifier, the register rename circuitry maps the selected architectural register specifier to the physical register indicated by the stored indication.

Abstract translation: 一种装置具有解码电路，用于对指令进行解码以产生微操作，以及寄存器重命名电路，以将由指令指定的架构寄存器指定符映射到物理寄存器以响应于微操作被访问。 响应于将所选择的架构寄存器说明符指定为源寄存器和目标寄存器的指令，解码电路将为其产生两个或多个微操作，寄存器重命名电路存储先前映射到 所选择的架构寄存器说明符。 响应于源寄存器对应于所选择的体系结构寄存器说明符的微操作之一，并且跟随目的寄存器对应于所选结构寄存器说明符的微操作，寄存器重命名电路映射所选择的架构寄存器 由存储的指示器指示的物理寄存器的说明符。

公开(公告)号：US20170123803A1

公开(公告)日：2017-05-04

申请号：US14927596

申请日：2015-10-30

Applicant: ARM Limited

Inventor： Karel Hubertus Gerardus WALTERS ,  Adam Raymond DULEY

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/328 ,  G06F9/3867

Abstract: An apparatus is provided comprising rewritable storage circuitry to store at least one mapping between at least one instruction identifier and a behaviour modification. Selection circuitry selects, from the rewritable storage circuitry, a selected mapping having an instruction identifier that identifies a received instruction. The received instruction causes a data processing unit to perform a default behaviour. Control circuitry causes the data processing unit to behave in accordance with the default behaviour modified by the behaviour modification.