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公开(公告)号：US20250004767A1
公开(公告)日：2025-01-02
申请号：US18345164
申请日：2023-06-30
Applicant: Arm Limited
IPC: G06F9/30
Abstract: Mode change detection circuitry detects a mode change when processing circuitry switches between first and second modes of processing in which a first set of architectural registers are designated as having different register lengths. Register mapping circuitry maps architectural registers to corresponding physical registers. For an operation specifying a given architectural register of the first set of architectural registers: in response to a determination that the operation is to be processed in the first mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a first physical register file, and in response to a determination that the operation is to be processed in the second mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a second physical register file separate from the first physical register file and having physical registers of different register length to physical registers of the first physical register file.
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公开(公告)号：US20220283847A1
公开(公告)日：2022-09-08
申请号：US17190729
申请日：2021-03-03
Applicant: Arm Limited
Inventor： Håkan Lars-Göran PERSSON , Frederic Claude Marie PIRY , Matthew Lucien EVANS , Albin Pierrick TONNERRE
Abstract: Apparatuses and methods are disclosed for performing data processing operations in main processing circuitry and delegating certain tasks to auxiliary processing circuitry. User-specified instructions executed by the main processing circuitry comprise a task dispatch specification specifying an indication of the auxiliary processing circuitry and multiple data words defining a delegated task comprising at least one virtual address indicator. In response to the task dispatch specification the main processing circuitry performs virtual-to-physical address translation with respect to the at least one virtual address indicator to derive at least one physical address indicator, and issues a task dispatch memory write transaction to the auxiliary processing circuitry comprises the indication of the auxiliary processing circuitry and the multiple data words, wherein the at least one virtual address indicator in the multiple data words is substituted by the at least one physical address indicator.
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公开(公告)号：US20240241723A1
公开(公告)日：2024-07-18
申请号：US18096141
申请日：2023-01-12
Applicant: Arm Limited
Inventor： Luca NASSI , Geoffray Matthieu LACOURBA , Cédric Denis Robert AIRAUD , Albin Pierrick TONNERRE
CPC classification number: G06F9/30098 , G06F9/30094 , G06F9/384
Abstract: A data processing apparatus is provided. Instruction send circuitry sends an instruction to an external processor to be executed by the external processor. Allocation circuitry allocates a specified one of several registers for a result of the instruction having been executed on the external processor and data receive circuitry receives the result of the instruction having been executed on the external processor and stores the result in the specified one of the several registers. In response to a condition being met: the specified one of the several registers is dereserved prior to the result being received by the data receive circuitry, and the result is discarded by the data receive circuitry when the result is received by the data receive circuitry.
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公开(公告)号：US20210311742A1
公开(公告)日：2021-10-07
申请号：US17266759
申请日：2019-07-17
Applicant: Arm Limited
Inventor： Peter Richard GREENHALGH , Frederic Claude Marie PIRY , Ian Michael CAULFIELD , Albin Pierrick TONNERRE
Abstract: An apparatus and method are provided for processing instructions. The apparatus has execution circuitry for executing instructions, where each instruction requires an associated operation to be performed using one or more source operand values in order to produce a result value. Issue circuitry is used to maintain a record of pending instructions awaiting execution by the execution circuitry, and prediction circuitry is used to produce a predicted source operand value for a chosen pending instruction. Optimisation circuitry is then arranged to detect an optimisation condition for the chosen pending instruction when the predicted source operand value is such that, having regard to the associated operation for the chosen pending instruction, the result value is known without performing the associated operation. In response to detection of the optimisation condition, an optimisation operation is implemented instead of causing the execution circuitry to perform the associated operation in order to execute the chosen pending instruction. This can lead to significant performance and/or power consumption improvements.
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5.发明申请公开(公告)号：US20210026635A1
公开(公告)日：2021-01-28
申请号：US16982300
申请日：2019-03-20
Applicant: Arm Limited
Inventor： Frederic Claude Marie PIRY , Peter Richard GREENHALGH , Ian Michael CAULFIELD , Albin Pierrick TONNERRE
IPC: G06F9/30 , G06F12/0875 , G06F12/0862 , G06F21/56 , G06F21/54 , G06F21/71
Abstract: An apparatus and method are provided for controlling allocation of instructions into an instruction cache storage. The apparatus comprises processing circuitry to execute instructions, fetch circuitry to fetch instructions from memory for execution by the processing circuitry, and an instruction cache storage to store instructions fetched from the memory by the fetch circuitry. Cache control circuitry is responsive to the fetch circuitry fetching a target instruction from a memory address determined as a target address of an instruction flow changing instruction, at least when the memory address is within a specific address range, to prevent allocation of the fetched target instruction into the instruction cache storage unless the fetched target instruction is at least one specific type of instruction. It has been found that such an approach can inhibit the performance of speculation-based caching timing side-channel attacks.
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Patent Agency Ranking
公开(公告)号：US20200065111A1
公开(公告)日：2020-02-27
申请号：US16106382
申请日：2018-08-21
Applicant: Arm Limited
Inventor： Houdhaifa BOUZGUARROU , Guillaume BOLBENES , Frederic Claude Marie PIRY , Albin Pierrick TONNERRE
Abstract: An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry for executing instructions, and branch prediction circuitry for making branch outcome predictions in respect of branch instructions. The branch prediction circuitry includes loop prediction circuitry having a plurality of entries, where each entry is used to maintain branch outcome prediction information for a loop controlling branch instruction that controls repeated execution of a loop comprising a number of instructions. The branch prediction circuitry is arranged to analyse blocks of instructions and to produce a prediction result for each block that is dependent on branch outcome predictions made for any branch instructions appearing in the associated block. A prediction queue then stores the prediction results produced by the branch prediction circuitry in order to determine the instructions to be executed by the processing circuitry. When the block of instructions being analysed comprises a loop controlling branch instruction that has an active entry in the loop prediction circuitry, and a determined condition is detected in respect of the associated loop, the loop prediction circuitry is arranged to produce a prediction result that identifies multiple iterations of the loop. This can significantly boost prediction bandwidth for certain types of loop.
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公开(公告)号：US20190163902A1
公开(公告)日：2019-05-30
申请号：US16149297
申请日：2018-10-02
Applicant: Arm Limited
Inventor： Alastair David REID , Dominic Phillip MULLIGAN , Milosch MERIAC , Matthias Lothar BOETTCHER , Nathan Yong Seng CHONG , Ian Michael CAULFIELD , Peter Richard GREENHALGH , Frederic Claude Marie PIRY , Albin Pierrick TONNERRE , Thomas Christopher GROCUTT , Yasuo ISHII
Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.
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公开(公告)号：US20210042227A1
公开(公告)日：2021-02-11
申请号：US16979624
申请日：2019-03-12
Applicant: Arm Limited
Inventor： Andreas Lars SANDBERG , Stephan DIESTELHORST , Nikos NIKOLERIS , Ian Michael CAULFIELD , Peter Richard GREENHALGH , Frederic Claude Marie PIRY , Albin Pierrick TONNERRE
IPC: G06F12/0802
Abstract: Coherency control circuitry (10) supports processing of a safe-speculative-read transaction received from a requesting master device (4). The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache (11) of the requesting master device (4) while prohibiting any change in coherency state associated with the target data in other caches (12) in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry (10) and the second cache (12) is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.
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公开(公告)号：US20210026641A1
公开(公告)日：2021-01-28
申请号：US17043963
申请日：2019-03-21
Applicant: Arm Limited
Inventor： Ian Michael CAULFIELD , Peter Richard GREENHALGH , Frederic Claude Marie PIRY , Albin Pierrick TONNERRE
IPC: G06F9/38 , G06F9/30 , G06F12/0891 , G06F12/0871
Abstract: An apparatus and method of operating a data processing apparatus are disclosed. The apparatus comprises data processing circuitry to perform data processing operations in response to a sequence of instructions, wherein the data processing circuitry is capable of performing speculative execution of at least some of the sequence of instructions. A cache structure comprising entries stores temporary copies of data items which are subjected to the data processing operations and speculative execution tracking circuitry monitors correctness of the speculative execution and responsive to indication of incorrect speculative execution to cause entries in the cache structure allocated by the incorrect speculative execution to be evicted from the cache structure.
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公开(公告)号：US20210019148A1
公开(公告)日：2021-01-21
申请号：US17041312
申请日：2019-03-14
Applicant: Arm Limited
Inventor： Ian Michael CAULFIELD , Peter Richard GREENHALGH , Frederic Claude Marie PIRY , Albin Pierrick TONNERRE
IPC: G06F9/38 , G06F12/0875
Abstract: Examples of the present disclosure relate to an apparatus comprising execution circuitry to execute instructions defining data processing operations on data items. The apparatus comprises cache storage to store temporary copies of the data items. The apparatus comprises prefetching circuitry to a) predict that a data item will be subject to the data processing operations by the execution circuitry by determining that the data item is consistent with an extrapolation of previous data item retrieval by the execution circuitry, and identifying that at least one control flow element of the instructions indicates that the data item will be subject to the data processing operations by the execution circuitry; and b) prefetch the data item into the cache storage.
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