公开(公告)号：US20180210731A1

公开(公告)日：2018-07-26

申请号：US15743735

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Mbou EYOLE ,  Alejandro MARTINEZ VICENTE

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/325

Abstract: Data processing apparatus comprises processing circuitry to selectively apply a vector processing operation to data items at positions within data vectors according to the states of a set of respective predicate flags associated with the positions, the data vectors having a data vector processing order, each data vector comprising a plurality of data items having a data item order, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inactive, all of the derived predicate flags in the set applicable to the current data vector are inactive.

公开(公告)号：US20190114172A1

公开(公告)日：2019-04-18

申请号：US16090357

申请日：2017-04-06

Applicant: ARM Limited

Inventor： Mbou EYOLE ,  Jacob EAPEN ,  Alejandro MARTINEZ VICENTE

IPC: G06F9/30 ,  G06F9/34

Abstract: An apparatus and method are provided for managing address collisions when performing vector operations. The apparatus has a register store for storing vector operands, each vector operand comprising a plurality of elements, and execution circuitry for executing instructions in order to perform operations specified by the instructions. The execution circuitry has access circuitry for performing memory access operations in order to move the vector operands between the register store and memory, and processing circuitry for performing data processing operations using the vector operands. The execution circuitry may be arranged to iteratively execute a vector loop, where during each iteration the execution circuitry executes a sequence of instructions to implement the vector loop. The sequence includes a check instruction identifying a plurality of memory addresses, and the execution circuitry is responsive to execution of the check instruction to determine whether an address hazard condition exists amongst the plurality of memory addresses. N For each iteration of the vector loop, the execution circuitry is responsive to execution of the check instruction determining an absence of the hazard address condition, to employ a default level of vectorisation when executing the sequence of instructions to implement the vector loop. In contrast, in the presence of the address hazard condition, the execution circuitry employs a reduced level of vectorisation when executing the sequence of instructions to implement the vector loop. Such an approach has been found to provide a low latency mechanism for dynamically adjusting the level of vectorisation employed during each iteration of the vector loop, enabling code to be vectorised whilst still enabling efficient performance in the presence of address hazard conditions.

公开(公告)号：US20190012176A1

公开(公告)日：2019-01-10

申请号：US15748734

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Grigorios MAGKLIS ,  Alejandro MARTINEZ VICENTE ,  Nathanael PREMILLIEU ,  Mbou EYOLE

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/3836

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.

公开(公告)号：US20180196673A1

公开(公告)日：2018-07-12

申请号：US15741303

申请日：2016-06-23

Applicant: ARM Limited

Inventor： Nigel John STEPHENS ,  Grigorios MAGKLIS ,  Alejandro MARTINEZ VICENTE ,  Nathanael PREMILLIEU

IPC: G06F9/30

Abstract: A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.