公开(公告)号：US20190303155A1

公开(公告)日：2019-10-03

申请号：US16468108

申请日：2017-11-10

Applicant: ARM LIMITED

Inventor： Jacob EAPEN ,  Grigorios MAGKLIS ,  Mbou EYOLE

IPC: G06F9/30 ,  G06F9/34

Abstract: A replicate elements instruction defining a plurality of variable length segments in a result vector controls processing circuitry (80) to generate a result vector in which, in each respective segment, a repeating value is repeated throughout that segment of the result vector, the repeating value comprising a data value or element index of a selected data element of a source vector. This instructions is useful for accelerating processing of data structures smaller than the vector length.

公开(公告)号：US20210141643A1

公开(公告)日：2021-05-13

申请号：US17258287

申请日：2019-05-09

Applicant: Arm Limited

Inventor： Matthew James HORSNELL ,  Grigorios MAGKLIS ,  Stephan DIESTELHORST

IPC: G06F9/30 ,  G06F9/38 ,  G06F13/16

Abstract: An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry. In response to a transactional compare-and-discard instruction executed within a given transaction, specifying a target address and a compare value, the processing circuitry loads a target data value from a memory location corresponding to the target address; sets at least one condition status indication depending on a result of comparing the target data value and the compare value; and discards the target data value without adding the target address to a working set of addresses tracked for the given transaction. This is useful for enabling thread level speculation to be implemented on a transactional memory architecture.

公开(公告)号：US20200167292A1

公开(公告)日：2020-05-28

申请号：US16625102

申请日：2018-06-01

Applicant: ARM LIMITED

Inventor： Matthew James HORSNELL ,  Grigorios MAGKLIS ,  Richard Roy GRISENTHWAITE

IPC: G06F12/1027 ,  G06F9/54 ,  G06F9/46 ,  G06F12/0873

Abstract: A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.

公开(公告)号：US20200278882A1

公开(公告)日：2020-09-03

申请号：US16651017

申请日：2018-08-21

Applicant: Arm Limited

Inventor： Matthew James HORSNELL ,  Grigorios MAGKLIS ,  Richard Roy GRISENTHWAITE ,  Stephan DIESTELHORST

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F11/14

Abstract: A data processing apparatus has processing circuitry with transactional memory support circuitry to support execution of a transaction using transactional memory. In response to an exception mask updating instruction which updates exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of a transaction, the processing circuitry permits un-aborted processing of one or more subsequent instruction of the transaction that follow the exception mask update instruction.

公开(公告)号：US20200225953A1

公开(公告)日：2020-07-16

申请号：US16629178

申请日：2018-06-27

Applicant: ARM LIMITED

Inventor： Grigorios MAGKLIS ,  Nigel John STEPHENS

IPC: G06F9/30

Abstract: An apparatus and method of operating an apparatus are provided. The apparatus is responsive to a bit-testing instruction which specifies a source vector register and an index to perform a bit-testing procedure on plural elements stored in the source vector register to generate plural result bits. The bit-testing procedure comprises, for each processed element of the plural elements, setting a respective result bit of the plural result bits in dependence on a value of a tested bit at a bit position in the processed element of the source vector register indicated by the index. This bit-testing instruction thus enables increased performance of program code which is required to perform multiple bit tests and can be suitably formulated into a vectorised form.

公开(公告)号：US20190171376A1

公开(公告)日：2019-06-06

申请号：US16309190

申请日：2017-05-18

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Grigorios MAGKLIS

IPC: G06F3/06 ,  G06F12/10 ,  G06F9/30

Abstract: A data processing apparatus and method serve to manage access permission checking in respect of contingent memory access operations (the access permission failure of which does not alter program flow) in dependence of a contingent-access permission checking disable flag. If the contingent access disable flag has a first value, then this disables memory permission circuitry e.g. a walk state machine 22, from performing a check as to whether or not the memory access circuitry is permitted to perform a requested memory access. Non-contingent memory accesses are able to utilise the memory permission circuitry irrespective of the value of the contingent-access permission checking disable flag.

公开(公告)号：US20210342152A1

公开(公告)日：2021-11-04

申请号：US17255001

申请日：2019-05-09

Applicant: Arm Limited

Inventor： Matthew James HORSNELL ,  Grigorios MAGKLIS ,  Richard Roy GRISENTHWAITE ,  Nathan Yong Seng CHONG

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread.

公开(公告)号：US20210103503A1

公开(公告)日：2021-04-08

申请号：US17046396

申请日：2019-04-08

Applicant: Arm Limited

Inventor： Matthew James HORSNELL ,  Grigorios MAGKLIS ,  Stephan DIESTELHORST

IPC: G06F11/14 ,  G06F9/46 ,  G06F11/07

Abstract: An apparatus and a method of operating a data processing apparatus, and simulators thereof, are disclosed. Data processing circuitry performs data processing operations in response to instructions, where some sets of instructions may be defined as a transaction which are to be performed atomically with respect to other operations performed by the data processing circuitry. When a synchronous exception occurs during a transaction the transaction is aborted and an exception counter is incremented. When the counter reaches a threshold value a transaction failure signal is generated, allowing, if appropriate a response to this number of exceptions causing transaction aborts to be carried out.

公开(公告)号：US20200257551A1

公开(公告)日：2020-08-13

申请号：US16651045

申请日：2018-08-21

Applicant: Arm Limited

Inventor： Grigorios MAGKLIS ,  Matthew James HORSNELL ,  Stephan DIESTELHORST

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/30 ,  G06F11/36

Abstract: In a system providing transactional memory support, a transaction nesting depth testing instruction is provided for triggering processing circuitry to set at least one status value to one of a plurality of states depending on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth is and at least one further state selected when the transaction nesting depth is greater than or less than. The ISA supported enables the setting of the at least one status value and a conditional branch conditional on the at least one status value being in the first state to be performed in response to a single transaction nesting depth testing instruction and a single conditional branch instruction.

公开(公告)号：US20200319885A1

公开(公告)日：2020-10-08

申请号：US16650999

申请日：2018-11-15

Applicant: Arm Limited

Inventor： Mbou EYOLE ,  Nigel John STEPHENS ,  Neil BURGESS ,  Grigorios MAGKLIS

IPC: G06F9/30 ,  G06F7/50

Abstract: Vector add-with-carry instructions are described which use some elements of a destination vector register, or corresponding fields of a predicate register, to provide the carry information corresponding to results of an add-with-carry operation. This is useful for accelerating computations involving multiplications of long integer values.