公开(公告)号：US20190243785A1

公开(公告)日：2019-08-08

申请号：US16386321

申请日：2019-04-17

Applicant: ARM Limited

Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Alessandro GRANDE

IPC: G06F13/14

CPC classification number: G06F13/14

Abstract: Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.

公开(公告)号：US20170012901A1

公开(公告)日：2017-01-12

申请号：US15273932

申请日：2016-09-23

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Alessandro GRANDE

IPC: H04L12/937 ,  H04L12/753

CPC classification number: G06F13/14

Abstract: Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection to provide said output following completion of and in dependence upon said arbitration.

Abstract translation: 用于在多个输入之间执行仲裁并选择所述多个输入中的至少一个以提供输出的仲裁和复用电路包括：具有X个仲裁级别的树状电路的仲裁，其中X是大于1的整数; 以及具有Y复用电平的复用树电路，其中Y是大于1的整数; 其中（i）所述Y复用电平包括在第二组所述多路复用电平上游的所述复用电平的第一集合; （ii）所述第一组所述复用级别被配置为与所述X个仲裁级别中的至少一些并行操作，由此所述第一组复用级别被配置为与由所述X仲裁执行的所述仲裁并行执行部分选择 水平; 和（iii）所述第二组所述复用级别被配置为与所述X个仲裁级别串联操作，由此所述第二组复用级别完成所述选择以在完成并根据所述仲裁之后提供所述输出。