公开(公告)号：US20160203093A1

公开(公告)日：2016-07-14

申请号：US14959170

申请日：2015-12-04

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Sean James SALISBURY ,  Daniel Adam SARA ,  George Robert Scott LLOYD

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F12/08

CPC classification number: G06F13/364 ,  G06F12/0815 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/621

Abstract: An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialise transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behaviour at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behaviour. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behaviour for those write transactions.

Abstract translation: 提供了用于连接多个主设备和多个从设备的互连的互连和操作方法。 危险管理电路用于将交易序列化到重叠地址。 另外，门控电路确保在与一个或多个主设备的接口上的有序写入观察（OWO）行为，门控电路接收写入事务的写入地址传输，并且执行门控操作以将写入地址传输的门向前传播到 从设备为了确保OWO的行为。 门控电路在危害管理电路的控制下执行门控操作。 因此，对于由危险管理电路进行危险检查的写入事务，这样就不需要实施任何其他进程来专门管理这些写入事务的OWO行为。

公开(公告)号：US20160062890A1

公开(公告)日：2016-03-03

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE ,  Jamshed JALAL ,  Mark David WERKHEISER ,  Arthur LAUGHTON ,  George Robert Scott LLOYD ,  Peter Andrew RIOCREUX ,  Daniel SARA

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。

公开(公告)号：US20140040516A1

公开(公告)日：2014-02-06

申请号：US13960128

申请日：2013-08-06

Applicant: ARM LIMITED

Inventor： Peter Andrew RIOCREUX ,  Bruce James MATHEWSON ,  Christopher William LAYCOCK ,  Richard Roy GRISENTHWAITE

IPC: G06F13/362

CPC classification number: G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

Abstract translation: 互连电路被配置为提供数据路由，至少一个发起者设备可经由该路由访问至少一个接收者设备。 所述电路包括：用于从至少一个发起者设备接收交易请求的至少一个输入; 用于向所述至少一个接收设备输出交易请求的至少一个输出; 以及用于在至少一个输入和至少一个输出之间传送事务请求的至少一个路径。 还包括用于将接收到的交易请求从至少一个输入路由到至少一个输出的控制电路，并且响应于屏障事务请求以维持关于业务流内的所述屏障事务请求的至少一些交易请求的排序 沿着所述至少一条路径中的一条通过的请求。 阻塞事务请求包括要保持其顺序的事务请求的指示符。

公开(公告)号：US20210303479A1

公开(公告)日：2021-09-30

申请号：US16834171

申请日：2020-03-30

Applicant: Arm Limited

Inventor： Peter Andrew RIOCREUX

IPC: G06F12/1045 ,  G06F12/0831 ,  G06F12/084 ,  G06F9/46

Abstract: Apparatus comprises address translation circuitry configured to access translation data defining a set of memory address translations; transaction handling circuitry to receive translation transactions and to receive invalidation transactions, each translation transaction defining one or more input memory addresses in an input memory address space to be translated to respective output memory addresses in an output memory address space, in which the transaction handling circuitry is configured to control the address translation circuitry to provide the output memory address as a translation response; in which each invalidation transaction defines at least a partial invalidation of the translation data; transaction tracking circuitry to associate an invalidation epoch, of a set of at least two invalidation epochs, with each translation transaction and with each invalidation transaction; and invalidation circuitry to store data defining a given invalidation transaction and, for translation transactions having the same invalidation epoch as the given invalidation transaction and handled by the address translation circuitry subsequent to the invalidation circuitry storing the data defining the given invalidation transaction, to process those translation transactions to indicate that a translation transaction is invalidated when the invalidation defined by the given invalidation transaction applies to that translation transaction; the invalidation circuitry being configured to forward at least an acknowledgement of the invalidation transaction for further processing by other apparatus in response to storage of the data by the invalidation circuitry.

公开(公告)号：US20150301961A1

公开(公告)日：2015-10-22

申请号：US14628331

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Daniel SARA ,  Sean James SALISBURY ,  Arthur LAUGHTON ,  Peter Andrew RIOCREUX

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/1673

Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialisation checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.

Abstract translation: 系统对核心集成电路2包括将多个事务源连接到多个事务目的地的互连电路4。 互连电路4包括用于缓冲访问事务的重新排序缓冲器和用于执行诸如点序列化检查和标识符重用检查的危险检查的危险检查电路46,48,50,52。 检查抑制电路62,64,66,68用于根据一个或多个状态变量来抑制一个或多个危险检查，所述一个或多个状态变量本身依赖于非危险检查或不被抑制的访问事务以外的访问事务。 作为示例，如果知道当前没有其他访问事务在重新排序缓冲器26内缓冲，或者替代地没有来自在重排序缓冲器26内缓冲的相同事务源的其他访问事务，则可以抑制危险检查。

公开(公告)号：US20210026568A1

公开(公告)日：2021-01-28

申请号：US16898781

申请日：2020-06-11

Applicant: Arm Limited

Inventor： Andrew Brookfield SWAINE ,  Peter Andrew RIOCREUX

IPC: G06F3/06 ,  G06F12/1027 ,  G06F12/1009

Abstract: An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point; and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.

公开(公告)号：US20190243785A1

公开(公告)日：2019-08-08

申请号：US16386321

申请日：2019-04-17

Applicant: ARM Limited

Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Alessandro GRANDE

IPC: G06F13/14

CPC classification number: G06F13/14

Abstract: Arbitrating circuitry arbitrates between a plurality of inputs and a selection of at least one of said plurality of inputs. The arbitrating circuitry includes an array of interconnected arbiter devices operating with respect to a set of Q inputs. The array comprises M sub-levels with at least a first sub-level having T arbiter devices each operating with respect to U inputs, where Q=UM and Q=TU. For each sub-level other than a first sub-level, each arbiter device in a sub-level receives as input requests signals indicating an arbitration outcome for two or more arbiter devices in a preceding sub-level and arbitrates between those input requests.

公开(公告)号：US20170012901A1

公开(公告)日：2017-01-12

申请号：US15273932

申请日：2016-09-23

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Peter Andrew RIOCREUX ,  Alessandro GRANDE

IPC: H04L12/937 ,  H04L12/753

CPC classification number: G06F13/14

Abstract: Arbitrating and multiplexing circuitry for performing an arbitration between a plurality of inputs and a selection of at least one of said plurality of inputs to provide an output comprises arbitrating tree circuitry having X arbitrating levels, where X is an integer greater than one; and multiplexing tree circuitry having Y multiplexing levels, where Y is an integer greater than one; wherein (i) said Y multiplexing levels comprise a first set of said multiplexing levels upstream of a second set of said multiplexing levels; (ii) said first set of said multiplexing levels is configured to operate in parallel with at least some of said X arbitrating levels, whereby said first set of multiplexing levels is configured to perform a partial selection in parallel with said arbitration performed by said X arbitrating levels; and (iii) said second set of said multiplexing levels is configured to operate in series with said X arbitrating levels, whereby said second set of multiplexing levels completes said selection to provide said output following completion of and in dependence upon said arbitration.

Abstract translation: 用于在多个输入之间执行仲裁并选择所述多个输入中的至少一个以提供输出的仲裁和复用电路包括：具有X个仲裁级别的树状电路的仲裁，其中X是大于1的整数; 以及具有Y复用电平的复用树电路，其中Y是大于1的整数; 其中（i）所述Y复用电平包括在第二组所述多路复用电平上游的所述复用电平的第一集合; （ii）所述第一组所述复用级别被配置为与所述X个仲裁级别中的至少一些并行操作，由此所述第一组复用级别被配置为与由所述X仲裁执行的所述仲裁并行执行部分选择 水平; 和（iii）所述第二组所述复用级别被配置为与所述X个仲裁级别串联操作，由此所述第二组复用级别完成所述选择以在完成并根据所述仲裁之后提供所述输出。

公开(公告)号：US20160103776A1

公开(公告)日：2016-04-14

申请号：US14874801

申请日：2015-10-05

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Arthur Brian LAUGHTON ,  Daniel Adam SARA ,  Sean James SALISBURY ,  Peter Andrew RIOCREUX

IPC: G06F13/364 ,  G06F15/78 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/4282

Abstract: Interconnect circuitry 10 for connecting transaction masters 4, 6, 8 to transaction slaves 12, 14 includes response modification circuitry 18. The response modification circuitry includes shortlist buffer circuitry 28 storing identification for modification target transaction responses. The response modification circuitry 18 uses this identification data to identify among a stream of transaction responses in transit a modification target transaction response. The response modification circuitry 18 then serves to form a modified transaction response to be sent in place of the modification target transaction response to the transaction master 4, 6, 8.

Abstract translation: 用于将交易主机4,6,8连接到交易从站12,14的互连电路10包括响应修改电路18.响应修改电路包括存储用于修改目标事务响应的标识的候选列表缓冲器电路28。 响应修改电路18使用该识别数据来识别传送中的事务响应流中的修改目标事务响应。 响应修改电路18然后用于形成被修改的事务响应，以代替对交易主机4,6,8的修改目标事务响应。