公开(公告)号：US09535700B2

公开(公告)日：2017-01-03

申请号：US13918664

申请日：2013-06-14

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt

IPC: G06F15/04 ,  G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3851

Abstract: A data processing system includes an execution pipeline that includes one or more programmable execution stages which execute execution threads to execute instructions to perform data processing operations. Instructions to be executed by a group of execution threads are first fetched into an instruction cache and then read from the instruction cache for execution by the thread group. When an instruction to be executed by a thread group is present in a cache line in the instruction cache, or is to be fetched into an allocated cache line in the instruction cache, a pointer to the location of the instruction in the instruction cache is stored for the thread group. This stored pointer is then used to retrieve the instruction for execution by the thread group from the instruction cache.

Abstract translation: 数据处理系统包括执行流水线，该执行流水线包括执行执行线程以执行指令以执行数据处理操作的一个或多个可编程执行阶段。 由一组执行线程执行的指令首先被提取到指令高速缓存中，然后从指令高速缓存读取以供线程组执行。 当指令高速缓存中的高速缓存线中存在要由线程组执行的指令，或者将其提取到指令高速缓存中的分配的高速缓存行时，存储指向高速缓存中指令位置的指针 为线程组。 然后，该存储的指针用于从指令高速缓存中检索线程组执行的指令。

公开(公告)号：US09514563B2

公开(公告)日：2016-12-06

申请号：US14015897

申请日：2013-08-30

Applicant: ARM Limited

Inventor： Sean Tristram Ellis ,  Jorn Nystad ,  Andreas Engh-Halstvedt

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T11/40

Abstract: When processing a set of tiles to generate an output in a tile based graphics processing pipeline, the pipeline, for one or more tiles of the set of tiles, renders one or more render targets containing data to be used in a processing operation (602), and stores the render targets in the tile buffer (604). It also stores some but not all of the sampling position values for a render target or targets for use when processing an adjacent tile of the set of tiles (606). It then performs a processing operation for the tile using the stored render target or targets (608) and one or more stored sampling position values from another, adjacent tile of the set of tiles (610), to generate an output for the tile (612).

Abstract translation: 当处理一组瓦片以在基于瓦片的图形处理流水线中生成输出时，对于该瓦片组的一个或多个瓦片，流水线呈现包含要在处理操作（602）中使用的数据的一个或多个渲染目标， 并将渲染目标存储在瓦片缓冲器（604）中。 当处理一组瓦片（606）的相邻瓦片时，它还存储一些而不是所有的渲染目标的采样位置值或用于使用的目标。 然后，它使用存储的渲染目标或目标（608）和来自瓦片组（610）的另一个相邻瓦片的一个或多个存储的采样位置值来执行瓦片的处理操作，以生成瓦片（612）的输出 ）。

公开(公告)号：US20150109313A1

公开(公告)日：2015-04-23

申请号：US14056727

申请日：2013-10-17

Applicant: ARM LIMITED

Inventor： Frode Heggelund ,  Andreas Engh-Halstvedt ,  Jorn Nystad ,  Henrik Ohlsson

IPC: G06T1/20

CPC classification number: G06T11/40 ,  G06T15/005 ,  G06T15/40

Abstract: Operating a graphics processing pipeline that includes processing stages including a rasteriser that rasterises input primitives to generate graphics fragments to be processed, each graphics fragment having one or more sampling points associated with it, and a renderer that processes fragments generated by the rasteriser to generate output fragment data for output to a render output, comprising the following steps: (i) determining first information to test whether at least a part of a primitive should be processed further; (ii) using at least some of the first information to decide whether to process at least a part of the primitive further; and if it is decided that at least a part of the primitive is to be processed further: (iii) determining further information to be used in further processing of the primitive; and (iv) further processing at least a part of the primitive using the determined further information.

Abstract translation: 操作图形处理流水线，其中包括处理阶段，包括栅格化输入基元以生成要处理的图形片段的光栅化器，每个图形片段具有与之相关联的一个或多个采样点;以及渲染器，其处理由光栅器产生的片段以产生输出 用于输出到渲染输出的片段数据，包括以下步骤：（i）确定第一信息以测试是否应进一步处理图元的至少一部分; （ii）使用所述第一信息中的至少一些来决定是否进一步处理所述原语的至少一部分; 并且如果确定要进一步处理所述原语的至少一部分：（iii）确定将用于进一步处理所述原语的另外的信息; 以及（iv）使用所确定的进一步的信息进一步处理所述原语的至少一部分。

公开(公告)号：US20140152684A1

公开(公告)日：2014-06-05

申请号：US13690159

申请日：2012-11-30

Applicant: ARM LIMITED

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Edvard Sorgard ,  Thomas Jeremy Olson ,  Marius Bjorge

IPC: G06T11/00

CPC classification number: G06T15/04 ,  G06T11/40

Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. Each page of a graphics texture has an associated fade factor value that can be set by an application that is to use the texture to control the contribution that the page will be used to make to any texturing result that is generated using the texture page in question. The graphics processing system then controls the contribution of texture data from a texture page to texturing result data to be generated in accordance with the fade factor value associated with the texture page in question. This allows texture paging to be done in a more visually pleasing manner than just a binary “page-is-here”/“page-is-not-here” switch.

Abstract translation: 图形虚拟纹理系统，其中存储在主机系统的存储介质中的纹理被划分为相应的页面，然后将其加载到图形处理系统的本地存储器中以供使用。 图形纹理的每个页面都具有相关联的渐变因子值，该值可由应用程序设置，该应用程序将使用纹理来控制页面将用于使用所讨论的纹理页面生成的任何纹理结果的贡献 。 图形处理系统然后根据与所讨论的纹理页面相关联的渐变因子值来控制纹理数据从纹理页面到纹理结果数据的贡献。 这允许纹理分页以更加视觉上令人愉快的方式来完成，而不仅仅是二进制“page-is-here”/“page-is-not-here”开关。

公开(公告)号：US09536333B2

公开(公告)日：2017-01-03

申请号：US14056727

申请日：2013-10-17

Applicant: ARM Limited

Inventor： Frode Heggelund ,  Andreas Engh-Halstvedt ,  Jorn Nystad ,  Henrik Ohlsson

IPC: G06T15/40 ,  G06T15/00 ,  G06T11/40

CPC classification number: G06T11/40 ,  G06T15/005 ,  G06T15/40

Abstract: Operating a graphics processing pipeline that includes processing stages including a rasteriser that rasterises input primitives to generate graphics fragments to be processed, each graphics fragment having one or more sampling points associated with it, and a renderer that processes fragments generated by the rasteriser to generate output fragment data for output to a render output, comprising the following steps: (i) determining first information to test whether at least a part of a primitive should be processed further; (ii) using at least some of the first information to decide whether to process at least a part of the primitive further; and if it is decided that at least a part of the primitive is to be processed further: (iii) determining further information to be used in further processing of the primitive; and (iv) further processing at least a part of the primitive using the determined further information.

Abstract translation: 操作图形处理流水线，其中包括处理阶段，包括栅格化输入基元以生成要处理的图形片段的光栅化器，每个图形片段具有与之相关联的一个或多个采样点;以及渲染器，其处理由光栅器产生的片段以产生输出 用于输出到渲染输出的片段数据，包括以下步骤：（i）确定第一信息以测试是否应进一步处理图元的至少一部分; （ii）使用所述第一信息中的至少一些来决定是否进一步处理所述原语的至少一部分; 并且如果确定要进一步处理所述原语的至少一部分：（iii）确定将用于进一步处理所述原语的另外的信息; 以及（iv）使用所确定的进一步的信息进一步处理所述原语的至少一部分。

公开(公告)号：US09417877B2

公开(公告)日：2016-08-16

申请号：US14299023

申请日：2014-06-09

Applicant: ARM Limited

Inventor： Simon Jones ,  Andreas Engh-Halstvedt ,  Aske Simon Christensen

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30189 ,  G06F9/30058 ,  G06F9/30145 ,  G06F9/3877

Abstract: An apparatus for processing data 2 is provided including processing circuitry 24 controlled by an instruction decoder 20 in response to a stream of program instructions. There is also provided dedicated function hardware 12 configured to receive output data from the processing circuitry and to perform a dedicated processing operation. The instruction decoder 20 is responsive to an end instruction 54 and a software processing flag (blend_shade_enabled) to control the processing circuitry to end a current software routine, to generate output data and in dependence upon the software processing flag either trigger processing of the output data by the dedicated function hardware or trigger the processing circuitry to perform a further software routine upon the output data to generate software generated result data instead of hardware generated result data as generated by the dedicated hardware circuitry.

Abstract translation: 提供了一种用于处理数据2的装置，其包括响应于程序指令流由指令解码器20控制的处理电路24。 还提供了专用功能硬件12，其被配置为从处理电路接收输出数据并执行专用处理操作。 指令解码器20响应于结束指令54和软件处理标志（blend_shade_enabled）来控制处理电路以结束当前软件程序，以产生输出数据，并根据软件处理标志触发输出数据的处理 通过专用功能硬件或触发处理电路，以在输出数据上执行另外的软件程序以产生软件产生的结果数据，而不是由专用硬件电路产生的硬件产生的结果数据。

公开(公告)号：US09349210B2

公开(公告)日：2016-05-24

申请号：US13690151

申请日：2012-11-30

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Edvard Sorgard ,  Thomas Jeremy Olson ,  Marius Bjorge

IPC: G09G5/00 ,  G06T15/04 ,  G06T1/60

CPC classification number: G06T15/04 ,  G06T1/60

Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. If the texture page that is required for performing a texturing operation at an originally desired level of detail (52) is not present in the local memory of the graphics processing system (53), the virtual texture lookup process loops back to try to sample the texture at an increased level of detail (55), and so on, until texture data that can be used is found in the local memory of the graphics processing system (53). This allows the texturing operation to proceed using texture data for the texel positions in question from a higher level (less detailed) mipmap in place of the originally desired texture data.

Abstract translation: 图形虚拟纹理系统，其中存储在主机系统的存储介质中的纹理被划分为相应的页面，然后将其加载到图形处理系统的本地存储器中以供使用。 如果在图形处理系统（53）的本地存储器中不存在用于以最初期望的细节级（52）执行纹理化操作所需的纹理页面，则虚拟纹理查找过程循环回来以尝试对 纹理处于增加的细节水平（55），等等，直到在图形处理系统（53）的本地存储器中找到可以使用的纹理数据。 这允许纹理化操作从较高级别（较不详细的）mipmap继续使用所讨论的纹素位置的纹理数据来代替原始期望的纹理数据。

公开(公告)号：US20140372731A1

公开(公告)日：2014-12-18

申请号：US13918664

申请日：2013-06-14

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3851

Abstract: A data processing system includes an execution pipeline that includes one or more programmable execution stages which execute execution threads to execute instructions to perform data processing operations. Instructions to be executed by a group of execution threads are first fetched into an instruction cache and then read from the instruction cache for execution by the thread group. When an instruction to be executed by a thread group is present in a cache line in the instruction cache, or is to be fetched into an allocated cache line in the instruction cache, a pointer to the location of the instruction in the instruction cache is stored for the thread group. This stored pointer is then used to retrieve the instruction for execution by the thread group from the instruction cache.

Abstract translation: 数据处理系统包括执行流水线，该执行流水线包括执行执行线程以执行指令以执行数据处理操作的一个或多个可编程执行阶段。 由一组执行线程执行的指令首先被提取到指令高速缓存中，然后从指令高速缓存读取以供线程组执行。 当指令高速缓存中的高速缓存线中存在要由线程组执行的指令，或者将其提取到指令高速缓存中的分配的高速缓存行时，存储指向高速缓存中指令位置的指针 为线程组。 然后，该存储的指针用于从指令高速缓存中检索线程组执行的指令。

公开(公告)号：US20140327684A1

公开(公告)日：2014-11-06

申请号：US13875831

申请日：2013-05-02

Applicant: ARM Limited

Inventor： Andreas Engh-Halstvedt

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06T11/40 ,  G09G5/02 ,  G09G5/39 ,  G09G2360/122 ,  G09G2360/127

Abstract: A tile-based graphics processing system comprises a host processor 1 and a graphics processing pipeline 3. The graphics processing pipeline 3 includes a rasteriser, a renderer, a tile buffer comprising an allocated amount of memory for use as the tile buffer, and a write out stage configured to write data stored in the tile buffer to an external memory. The driver 4 for the graphics processing pipeline 3 on the host processor 1 determines the tile data storage requirements for each render target to be generated for a render output to be generated by the graphics processing system and allocates portions of the memory allocated for use as the tile buffer to respective ones of the render targets based on the determination.

Abstract translation: 基于瓦片的图形处理系统包括主机处理器1和图形处理流水线3.图形处理流水线3包括光栅化器，渲染器，包括用作片缓冲器的分配量的存储器的片缓冲器，以及写 输出级被配置为将存储在瓦片缓冲器中的数据写入外部存储器。 用于主机处理器1上的图形处理流水线3的驱动器4确定要由图形处理系统生成的渲染输出生成的每个渲染目标的瓦片数据存储需求，并且将分配用于作为 基于该确定，将缓冲区分配给各个渲染目标。

公开(公告)号：US09779536B2

公开(公告)日：2017-10-03

申请号：US14790452

申请日：2015-07-02

Applicant: ARM Limited

Inventor： Andreas Engh-Halstvedt ,  Daren Croxford ,  Frank Langtind

IPC: G06T15/50 ,  G06T15/00

CPC classification number: G06T15/005

Abstract: A graphics processing pipeline (20) comprises first vertex shading circuitry (21) that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline. Tiling circuitry (22) then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. A second vertex shading circuitry (23) then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further.