公开(公告)号：US20150049563A1

公开(公告)日：2015-02-19

申请号：US13967879

申请日：2013-08-15

Applicant: ARM LIMITED

Inventor： Bikas MAITI ,  Yew Keong CHONG ,  Martin Jay KINKADE

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C5/148 ,  G11C7/227 ,  G11C11/419

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. Access circuitry is coupled to the word lines and the bit lines in order to perform access operations in respect of selected memory cells within the array. Control circuitry controls operation of the access circuitry and includes self-timed path (STP) delay circuitry. The control circuitry employs the delay indication when controlling the access circuitry to perform said access operations. Voltage supply control circuitry switches the voltage supply to at least one portion of the STP delay circuitry between a peripheral voltage supply and an array voltage supply dependent on a control signal.

Abstract translation: 存储器件包括布置成多个行和列的存储器单元的阵列，多个字线，每个字线耦合到相关行的存储器单元，以及多个位线，每个位线耦合到 相关的存储单元列。 访问电路被耦合到字线和位线，以便对阵列内的所选存储单元执行访问操作。 控制电路控制接入电路的操作，并且包括自定时路径（STP）延迟电路。 控制电路在控制访问电路执行所述访问操作时采用延迟指示。 电压供应控制电路根据控制信号将外部电压源和阵列电压电源之间的电压供应切换到STP延迟电路的至少一部分。