公开(公告)号：US09070431B2

公开(公告)日：2015-06-30

申请号：US14063612

申请日：2013-10-25

Applicant: ARM LIMITED

Inventor： Frank Guo ,  Martin Jay Kinkade ,  Bo Zheng ,  Brian Reed ,  Shrisagar Dwivedi

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/222 ,  G11C11/419

Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

Abstract translation: 存储器电路具有用于在写入操作期间产生较低电源电压的写辅助电路。 写辅助电路包括多个串联连接的交换机，包括头部交换机和页脚开关。 标题偏置电路产生标题偏置电压，页脚偏置电路产生页脚偏置电压。 标头偏置电压是具有在电源电压电平和接地电压电平之间的电压电平的模拟信号。 页脚偏置电压是一个模拟信号，其电压电平介于电源电压电平和接地电压电平之间。 在写操作期间，要写入的目标比特单元通过头部开关经由电流路径被提供，同时它们分别由头部偏置电压和页脚偏置电压控制。

公开(公告)号：US20150117119A1

公开(公告)日：2015-04-30

申请号：US14063612

申请日：2013-10-25

Applicant: ARM LIMITED

Inventor： Frank GUO ,  Martin Jay Kinkade ,  Bo Zheng ,  Brian Reed ,  Shrisagar Dwivedi

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/222 ,  G11C11/419

Abstract: Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.

Abstract translation: 存储器电路具有用于在写入操作期间产生较低电源电压的写辅助电路。 写辅助电路包括多个串联连接的交换机，包括头部交换机和页脚开关。 标题偏置电路产生标题偏置电压，页脚偏置电路产生页脚偏置电压。 标头偏置电压是具有在电源电压电平和接地电压电平之间的电压电平的模拟信号。 页脚偏置电压是一个模拟信号，其电压电平介于电源电压电平和接地电压电平之间。 在写操作期间，要写入的目标比特单元通过头部开关经由电流路径被提供，同时它们分别由头部偏置电压和页脚偏置电压控制。