公开(公告)号：US09304926B2

公开(公告)日：2016-04-05

申请号：US13948658

申请日：2013-07-23

Applicant: ARM LIMITED

Inventor： Ian Bratt ,  Mladen Wilder ,  Ole Henrik Jahren

IPC: G06F12/08

CPC classification number: G06F12/0855 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  Y02D10/13

Abstract: A coherent memory system includes a plurality of level 1 cache memories 6 connected via interconnect circuitry 18 to a level 2 cache memory 8. Coherency control circuitry 10 manages coherency between lines of data. Evict messages from the level 1 cache memories to the coherency control circuitry 10 are sent via the read address channel AR. Read messages are also sent via the read address channel AR. The read address channel AR is configured such that a read message may not be reordered relative to an evict message. The coherency control circuitry 10 is configured such that a read message will not be processed ahead of an evict message. The level 1 cache memories 6 do not track in-flight evict messages. No acknowledgement of an evict message is sent from the coherency control circuitry 10 back to the level 1 cache memory 6.

Abstract translation: 相干存储器系统包括经由互连电路18连接到级别2高速缓冲存储器8的多个1级高速缓冲存储器6。一致性控制电路10管理数据线之间的相干性。 通过读地址信道AR发送从1级缓存存储器到相干性控制电路10的消息。 读消息也通过读地址通道AR发送。 读地址信道AR被配置为使得读消息可能不相对于逐出消息重新排序。 一致性控制电路10被配置为使得读取消息将不会在逐出消息之前被处理。 级别1缓存存储器6不跟踪飞行中的逐出消息。 从相关性控制电路10不发送逐出消息的确认回到1级缓存存储器6。

公开(公告)号：US10078589B2

公开(公告)日：2018-09-18

申请号：US14700259

申请日：2015-04-30

Applicant: ARM LIMITED

Inventor： Daniel Sara ,  Antony John Harris ,  Håkan Lars-Göran Persson ,  Andrew Christopher Rose ,  Ian Bratt

IPC: G06F12/08 ,  G06F12/14 ,  G06F12/0831

CPC classification number: G06F12/0831 ,  G06F12/0833 ,  G06F12/1491 ,  G06F2212/1052

Abstract: Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.