公开(公告)号：US20250110874A1

公开(公告)日：2025-04-03

申请号：US18476659

申请日：2023-09-28

Applicant: Arm Limited

Inventor： Fabrice Jean VERPLANKEN ,  Rakesh RAMAN ,  Nikita PrakashChandra BHANDARI

IPC: G06F12/0808 ,  G06F12/02 ,  G06F13/18

Abstract: Cache invalidation circuitry responds to a cache invalidation command specifying invalidation scope information indicative of at least one invalidation condition, to control a cache to perform an invalidation process to invalidate cache entries satisfying the invalidation condition(s). Cache lookup circuitry issues to the cache a cache lookup request specifying address information, to request that the cache returns a cache lookup response. Cache lookup response filtering circuitry is responsive to a given hit-indicating cache lookup response which provides cached information and invalidation qualifying information returned from a corresponding valid cache entry, to determine whether the given hit-indicating cache lookup response conflicts with an in-progress cache invalidation command, based on the invalidation scope information specified by the in-progress cache invalidation command and the invalidation qualifying information, and when conflict is detected, causes the given hit-indicating cache lookup response to be treated as a miss-indicating cache lookup response.

公开(公告)号：US20160014050A1

公开(公告)日：2016-01-14

申请号：US14734367

申请日：2015-06-09

Applicant: ARM LIMITED

Inventor： Rakesh RAMAN ,  Andrew David TUNE ,  Guanghui GENG

IPC: H04L12/937 ,  H04L12/753

CPC classification number: H04L45/48 ,  G06F13/14

Abstract: Arbitrating and multiplexing circuitry 28 comprises arbitrating tree circuitry having X arbitrating levels and multiplexing tree circuitry having Y multiplexing levels. The Y multiplexing levels comprise a first set of multiplexing levels upstream of a second set of multiplexing levels. The first set of multiplexing levels operate in parallel with at least some of the arbitrating levels. The second set of multiplexing levels operate in series with the X arbitrating levels such that the second set of multiplexing levels completes the required selection to provide the final output following completion of, and in dependence upon, the arbitration by the arbitrating tree circuitry.

Abstract translation: 仲裁和复用电路28包括具有X个仲裁级别的树电路的仲裁和具有Y复用级别的复用树电路。 Y复用级别包括第二组复用级别上游的第一组复用级别。 第一组复用级别与至少一些仲裁级别并行操作。 第二组复用电平与X仲裁电平串联操作，使得第二组复用电平完成所需的选择，以在完成仲裁树电路并根据仲裁树电路的仲裁之后提供最终输出。