公开(公告)号：US20230401667A1

公开(公告)日：2023-12-14

申请号：US18249342

申请日：2021-10-19

Applicant: Arm Limited

Inventor： Sandeep KAKARLAPUDI ,  Andreas ENGH-HALSTVEDT ,  Frank Klaeboe LANGTIND

IPC: G06T1/20 ,  G06T15/40 ,  G06T11/40

CPC classification number: G06T1/20 ,  G06T15/40 ,  G06T11/40 ,  G06T2210/12

Abstract: A method of operating a graphics processor to process sets of geometry to generate an output. Each set of geometry is associated with lower level geometry including vertex data to be used when rendering the geometry as well a separate higher level representation of the geometry. The higher level representations of the geometry can be obtained by the graphics processor independently of the other, lower level geometry and used to determine which sets of geometry should be processed for which regions of the output. Once this determination is made, the regions can be rendered by obtaining and processing the lower level geometry accordingly.

公开(公告)号：US20220358616A1

公开(公告)日：2022-11-10

申请号：US17662350

申请日：2022-05-06

Applicant: Arm Limited

Inventor： Toni Viki BRKIC ,  Sandeep KAKARLAPUDI ,  Tord Kvestad ØYGARD ,  Saurav ARJUN

IPC: G06T1/20 ,  G06T1/60

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline that includes an early culling tester that can access plural different culling test data buffers is disclosed. Information is maintained indicating which of the plural culling test data buffers is expected to be accessed, and the information is used to control the early culling tester. The information may be used to control the early culling tester such that processing delays associated with waiting for dependencies to resolve are reduced.

公开(公告)号：US20130155103A1

公开(公告)日：2013-06-20

申请号：US13658997

申请日：2012-10-24

Applicant: ARM LIMITED

Inventor： Sandeep KAKARLAPUDI ,  Jorn NYSTAD

IPC: G09G5/377

CPC classification number: G09G5/377 ,  G06T11/40 ,  G06T15/005 ,  G09G5/363 ,  G09G2360/06 ,  G09G2360/122

Abstract: A tile-based graphics processor includes tile processing circuitry that has both a tile buffer and a per-pixel general purpose data store. The per-pixel general purpose data store is read accessible and write accessible by the tile processing circuitry to store intermediate values. These intermediate values are generated by the tile processing circuitry and then consumed by the tile processing circuitry to generate the output values for the tile being processed.

Abstract translation: 基于瓦片的图形处理器包括具有瓦片缓冲器和每像素通用数据存储器的瓦片处理电路。 每像素通用数据存储器被读取可访问并且可由片处理电路写入以存储中间值。 这些中间值由瓦片处理电路产生，然后由瓦片处理电路消耗以产生正被处理的瓦片的输出值。