IN-CORE PARALLELISATION IN A DATA PROCESSING APPARATUS AND METHOD

    公开(公告)号:US20230325194A1

    公开(公告)日:2023-10-12

    申请号:US18042845

    申请日:2021-08-26

    Applicant: ARM LIMITED

    CPC classification number: G06F9/3851 G06F9/3016

    Abstract: A data processing apparatus and a method for processing data are disclosed. The data processing apparatus comprises: multithreaded processing circuitry to perform processing operations of a plurality of micro-threads, each micro-thread operating in a corresponding execution context defining an architectural state. Thread control circuitry collects runtime data indicative of a performance metric relating to the processing operations. Decoder circuitry is responsive to a detach instruction in a first micro-thread of instructions executed in a first execution context defining a first architectural state, the detach instruction specifying an address, to provide detach control signals to the thread control circuitry. When the runtime data meet a parallelisation criterion, the thread control circuitry is responsive to the detach control signals to spawn a second micro-thread of instructions executed in a second execution context defining a second architectural state based on the first architectural state, the second micro-thread of instructions comprising a subset of instructions of the first micro-thread of instructions starting at the address.

    CIRCUITRY AND METHODS
    2.
    发明申请

    公开(公告)号:US20210124585A1

    公开(公告)日:2021-04-29

    申请号:US16662396

    申请日:2019-10-24

    Applicant: Arm Limited

    Abstract: Circuitry comprises decode circuitry to decode program instructions including producer instructions and consumer instructions, a consumer instruction requiring, as an input operand, a result generated by execution of a producer instruction; and execution circuitry to execute the program instructions; in which: the decode circuitry is configured to control operation of the execution circuitry in response to hint data associated with a given producer instruction and indicating, for the given producer instruction, a number of consumer instructions which require, as an input operand, a result generated by the given producer instruction.

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