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公开(公告)号：US20230325194A1
公开(公告)日：2023-10-12
申请号：US18042845
申请日：2021-08-26
Applicant: ARM LIMITED
Inventor： Syed Ali Mustafa ZAIDI , Giacomo GABRIELLI
CPC classification number: G06F9/3851 , G06F9/3016
Abstract: A data processing apparatus and a method for processing data are disclosed. The data processing apparatus comprises: multithreaded processing circuitry to perform processing operations of a plurality of micro-threads, each micro-thread operating in a corresponding execution context defining an architectural state. Thread control circuitry collects runtime data indicative of a performance metric relating to the processing operations. Decoder circuitry is responsive to a detach instruction in a first micro-thread of instructions executed in a first execution context defining a first architectural state, the detach instruction specifying an address, to provide detach control signals to the thread control circuitry. When the runtime data meet a parallelisation criterion, the thread control circuitry is responsive to the detach control signals to spawn a second micro-thread of instructions executed in a second execution context defining a second architectural state based on the first architectural state, the second micro-thread of instructions comprising a subset of instructions of the first micro-thread of instructions starting at the address.
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2.发明申请公开(公告)号：US20150227367A1
公开(公告)日：2015-08-13
申请号：US14175268
申请日：2014-02-07
Applicant: ARM LIMITED
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F9/30014 , G06F9/30072 , G06F9/30076 , G06F9/30098 , G06F9/3887 , G06F9/3891
Abstract: A data processing apparatus and method are provided for performing segmented operations. The data processing apparatus comprises a vector register store for storing vector operands, and vector processing circuitry providing N lanes of parallel processing, and arranged to perform a segmented operation on up to N data elements provided by a specified vector operand, each data element being allocated to one of the N lanes. The up to N data elements forms a plurality of segments, and performance of the segmented operation comprises performing a separate operation on the data elements of each segment, the separate operation involving interaction between the lanes containing the data elements of the associated segment. Predicate generation circuitry is responsive to a compute descriptor instruction specifying an input vector operand comprising a plurality of segment descriptors, to generate per lane predicate information used by the vector processing circuitry when performing the segmented operation to maintain a boundary between each of the plurality of segments. As a result, interaction between lanes containing data elements from different segments is prevented. This allows very effective utilisation of the lanes of parallel processing within the vector processing circuitry to be achieved.
Abstract translation: 提供了一种用于执行分段操作的数据处理装置和方法。 数据处理装置包括用于存储向量操作数的向量寄存器存储器和提供N个并行处理通道的向量处理电路，并且被布置为对由指定向量操作数提供的多达N个数据元素执行分段操作，每个数据元素被分配 到N条车道之一。 最多N个数据元素形成多个段，并且分段操作的执行包括对每个段的数据元素执行单独的操作，该单独操作涉及包含相关段的数据元素的通道之间的交互。 谓词生成电路响应于指定包括多个段描述符的输入向量操作数的计算描述符指令，以在执行分割操作时生成由向量处理电路使用的每通道谓词信息，以维持多个段中的每个段之间的边界 。 结果，阻止了包含来自不同段的数据元素的通道之间的相互作用。 这允许在矢量处理电路内非常有效地利用并行处理的通道。
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公开(公告)号：US20240086196A1
公开(公告)日：2024-03-14
申请号：US17941387
申请日：2022-09-09
Applicant: Arm Limited
Inventor： Matthew James WALKER , Mbou EYOLE , Giacomo GABRIELLI , Balaji VENU
CPC classification number: G06F9/30123 , G06F9/4881
Abstract: There is provided an apparatus, method and medium for data processing. The apparatus comprises a register file comprising a plurality of data registers, and frontend circuitry responsive to an issued instruction, to control processing circuitry to perform a processing operation to process an input data item to generate an output data item. The processing circuitry is responsive to a first encoding of the issued instruction specifying a data register, to read the input data item from the data register, and/or write the output data item to the data register. The processing circuitry is responsive to a second encoding of the issued instruction specifying a buffer-region of the register file for storing a queue of data items, to perform the processing operation and to perform a dequeue operation to dequeue the input data item from the queue, and/or perform an enqueue operation to enqueue the output data item to the queue.
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公开(公告)号：US20210342248A1
公开(公告)日：2021-11-04
申请号：US17271399
申请日：2019-08-30
Applicant: Arm Limited
Inventor： Timothy HAYES , Giacomo GABRIELLI , Matthew James HORSNELL
Abstract: An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals. Further, history analysis circuitry is responsive to an analysis trigger to analyse the event history information in order to detect a reporting condition when the event history information indicates that a ratio between occurrences of the first event and the occurrences of the second event is outside an acceptable range. The history analysis circuitry is then responsive to detection of the reporting condition to assert a report signal. This provides a particularly efficient and effective mechanism for monitoring ratios of events within a data processing system.
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5.发明申请公开(公告)号：US20150254076A1
公开(公告)日：2015-09-10
申请号：US14601431
申请日：2015-01-21
Applicant: ARM LIMITED
Inventor： Matthias BOETTCHER , Giacomo GABRIELLI , Mbou EYOLE-MONONO
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F9/3001 , G06F9/30098
Abstract: A vector scan operation is performed to generate M data elements of a result vector, where each result data element corresponds to a combination of an additional data element with at least some of the data elements of a source vector operand V. The vector scan operation is performed using a plurality of steps, each step comprising one or more combination operations for combining data elements. At least one of the steps includes two or more combination operations performed in parallel. At least two of the steps comprise a combination operation for combining a data element with the additional data element S. This approach enables the vector scan operation to be performed in fewer steps in the case where fewer than M data elements are active, so that the vector scan operation can be performed more quickly.
Abstract translation: 执行矢量扫描操作以产生结果矢量的M个数据元素，其中每个结果数据元素对应于附加数据元素与源向量操作数V的至少一些数据元素的组合。矢量扫描操作是 使用多个步骤执行，每个步骤包括用于组合数据元素的一个或多个组合操作。 至少一个步骤包括并行执行的两个或多个组合操作。 至少两个步骤包括用于将数据元素与附加数据元素S组合的组合操作。在少于M个数据元素有效的情况下，该方法使得能够以更少的步骤执行向量扫描操作，使得 可以更快地执行向量扫描操作。
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Patent Agency Ranking
公开(公告)号：US20240086201A1
公开(公告)日：2024-03-14
申请号：US17941404
申请日：2022-09-09
Applicant: Arm Limited
Inventor： Matthew James WALKER , Mbou EYOLE , Giacomo GABRIELLI , Balaji VENU
IPC: G06F9/38
CPC classification number: G06F9/3855 , G06F9/3802
Abstract: One or more triggered-instruction processing elements are provided, a given triggered-instruction processing element comprising execution circuitry to execute processing operations in response to instructions according to a triggered instruction architecture. Input channel processing circuitry receives a given tagged data item (comprising a data value and a tag value) for a given input channel, and in response controls enqueuing of the data value of the given tagged data item to a selected buffer structure selected from among at least two buffer structures mapped onto register storage accessible to one or more of the triggered-instruction processing elements in response to a computation instruction for controlling performance of a computation operation. The selected buffer structure is selected based at least on the tag value, so data values of tagged data items specifying different tag values for the given input channel are allocatable to different buffer structures.
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公开(公告)号：US20190205140A1
公开(公告)日：2019-07-04
申请号：US16208701
申请日：2018-12-04
Applicant: Arm Limited
Inventor： Richard Roy GRISENTHWAITE , Giacomo GABRIELLI , Matthew James HORSNELL
IPC: G06F9/30
CPC classification number: G06F9/30196 , G06F9/30018 , G06F9/30032 , G06F9/30036
Abstract: An apparatus comprises processing circuitry to perform data processing and instruction decoding circuitry to decode instructions to control the processing circuitry to perform the data processing. The instruction decoding circuitry is responsive to a speculation barrier instruction to control the processing circuitry to prevent a subsequent operation, appearing in program order after the speculation barrier instruction, that has an address dependency on an earlier instruction preceding the speculation barrier instruction in the program order, from speculatively influencing allocations of entries in a cache. This provides protection against speculative cache-timing side-channel attacks.
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公开(公告)号：US20180293078A1
公开(公告)日：2018-10-11
申请号：US15769558
申请日：2016-09-14
Applicant: ARM LIMITED
Inventor： Giacomo GABRIELLI , Nigel John STEPHENS
CPC classification number: G06F9/3865 , G06F9/3001 , G06F9/30036
Abstract: Processing circuitry supports a first type of vector arithmetic instruction specifying at least a first input vector. When at least one exceptional condition is detected for an arithmetic operation performed for a first active data element of the first input vector in a predetermined sequence, the processing circuitry performs at least one response action. When the at least one exceptional condition is detected for a given active data element other than the first active data element in the predetermined sequence, the processing circuitry suppresses the at least one response action and stores elements identifying information identifying which data element is the given active data element which triggered the exceptional condition. This can be useful for reducing the amount of hardware resource for tracking the occurrence of the exceptional conditions and/or supporting speculative execution of vector instructions.
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公开(公告)号：US20150212972A1
公开(公告)日：2015-07-30
申请号：US14165967
申请日：2014-01-28
Applicant: ARM LIMITED
Inventor： Matthias Lothar BOETTCHER , Mbou EYOLE-MONONO , Giacomo GABRIELLI
CPC classification number: G06F15/78 , G06F9/3001 , G06F9/30036 , G06F9/30098 , G06F9/3017 , G06F9/3875 , G06F9/3887 , G06F9/3893
Abstract: A data processing apparatus and method are provided for executing a vector scan instruction. The data processing apparatus comprises a vector register store configured to store vector operands, and processing circuitry configured to perform operations on vector operands retrieved from said vector register store. Further, control circuitry is configured to control the processing circuitry to perform the operations required by one or more instructions, said one or more instructions including a vector scan instruction specifying a vector operand comprising N vector elements and defining a scan operation to be performed on a sequence of vector elements within the vector operand. The control circuitry is responsive to the vector scan instruction to partition the N vector elements of the specified vector operand into P groups of adjacent vector elements, where P is between 2 and N/2, and to control the processing circuitry to perform a partitioned scan operation yielding the same result as the defined scan operation. The processing circuitry is configured to perform the partitioned scan operation by performing separate scan operations on those vector elements of the sequence contained within each group to produce intermediate results for each group, and to perform a computation operation to combine the intermediate results into a final result vector operand containing a sequence of result vector elements. The partitioned scan operation approach of the present invention enables a balance to be achieved between energy consumption and performance.
Abstract translation: 提供了一种用于执行向量扫描指令的数据处理装置和方法。 数据处理装置包括被配置为存储向量操作数的向量寄存器存储器，以及被配置为对从所述向量寄存器存储器检索的向量操作数执行操作的处理电路。 此外，控制电路被配置为控制处理电路执行一个或多个指令所需的操作，所述一个或多个指令包括指定包括N个向量元素的向量操作数的向量扫描指令，并且定义要在 向量操作数中向量元素的序列。 控制电路响应于矢量扫描指令将指定矢量操作数的N个向量元素划分为相邻矢量元素的P组，其中P在2和N / 2之间，并且控制处理电路执行分区扫描 操作产生与定义的扫描操作相同的结果。 处理电路被配置为通过对包含在每个组中的序列的那些矢量元素执行单独的扫描操作来执行分割扫描操作，以产生每个组的中间结果，并且执行计算操作以将中间结果组合成最终结果 向量操作数包含一系列结果向量元素。 本发明的划分扫描操作方法能够在能量消耗和性能之间实现平衡。
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公开(公告)号：US20250036632A1
公开(公告)日：2025-01-30
申请号：US18226334
申请日：2023-07-26
Applicant: Arm Limited
Inventor： Damian Piotr MODRZYK , Metin Gokhan ÜNAL , Giacomo GABRIELLI , Balaji VENU
IPC: G06F16/2455 , G06F16/2453
Abstract: Provided is a data stream processor comprising a streamed data transceiver interface, a structure of processing units configurable to transform data received from a data source over the streamed data transceiver interface according to a specified output requirement, and a configuration unit operable in electronic communication with a data consumer to receive an output requirement and to configure the operation and linkage of a processing unit in the structure of processing units to transform input data to output data according to the specified output requirement; wherein the structure of processing units is further operable to provide the output data for output over the streamed data transceiver interface.
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