公开(公告)号：US20200257841A1

公开(公告)日：2020-08-13

申请号：US16861286

申请日：2020-04-29

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar SINHA ,  Kyungwook CHANG ,  Brian Tracy CLINE ,  Ebbin Raney SOUTHERLAND, JR.

IPC: G06F30/34 ,  G06F30/3312 ,  G06F30/394 ,  G06F30/392

Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

公开(公告)号：US20180060475A1

公开(公告)日：2018-03-01

申请号：US15252592

申请日：2016-08-31

Applicant: ARM LIMITED

Inventor： Saurabh Pijuskumar SINHA ,  Kyungwook CHANG ,  Brian Tracy CLINE ,  Ebbin Raney SOUTHERLAND, JR.

IPC: G06F17/50

Abstract: A method for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

公开(公告)号：US20150226800A1

公开(公告)日：2015-08-13

申请号：US14175015

申请日：2014-02-07

Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN ,  ARM LIMITED

Inventor： Yejoong KIM ,  Dennis Michael SYLVESTER ,  David Theodore BLAAUW ,  Brian Tracy CLINE

IPC: G01R31/317 ,  H03K3/03

CPC classification number: G01R31/31725 ,  H03K3/0315

Abstract: A measurement circuit and method are provided for measuring a clock node to output node delay of a flip-flop. A main ring oscillator has a plurality of main unit cells arranged in a ring, with each main unit cell comprising a flip-flop and pulse generation circuitry connected to the output node of the flip-flop. The flip-flop is responsive to receipt of an input clock pulse at the clock node to output a data value transition from the output node, and the pulse generation circuitry then generates from the data value transition an input clock pulse for a next main unit cell in the main ring, whereby the main ring oscillator generates a first output signal having a first oscillation period. A reference ring oscillator has a plurality of reference unit cells arranged to form a reference ring, and generates a second output signal having a second oscillation period, each reference unit cell comprising components configured such that the second oscillation period provides an indication of a propagation delay through the pulse generation circuitry of the main unit cells of the main ring during the first oscillation period. Calculation circuitry then determines the clock node to output node delay of the flip-flop from the first oscillation period and the second oscillation period. This provides a particularly simple and accurate mechanism for calculating the clock node to output node delay of a flip-flop.

Abstract translation: 提供了一种用于测量时钟节点以输出触发器的节点延迟的测量电路和方法。 主环形振荡器具有以环形排列的多个主单元，每个主单元包括连接到触发器的输出节点的触发器和脉冲发生电路。 触发器响应于在时钟节点处接收到输入时钟脉冲，以从输出节点输出数据值转换，然后脉冲产生电路从数据值转换下一个主单位单元的输入时钟脉冲 在主环中，由此主环形振荡器产生具有第一振荡周期的第一输出信号。 参考环形振荡器具有布置成形成参考环的多个参考单元，并且产生具有第二振荡周期的第二输出信号，每个参考单元包括被配置为使得第二振荡周期提供传播延迟的指示 通过第一振荡周期内主环的主单元的脉冲发生电路。 计算电路然后确定时钟节点以从第一振荡周期和第二振荡周期输出触发器的节点延迟。 这提供了用于计算时钟节点以输出触发器的节点延迟的特别简单且准确的机制。