公开(公告)号：US20200257841A1

公开(公告)日：2020-08-13

申请号：US16861286

申请日：2020-04-29

Applicant: ARM Limited

Inventor： Saurabh Pijuskumar SINHA ,  Kyungwook CHANG ,  Brian Tracy CLINE ,  Ebbin Raney SOUTHERLAND, JR.

IPC: G06F30/34 ,  G06F30/3312 ,  G06F30/394 ,  G06F30/392

Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

公开(公告)号：US20180060475A1

公开(公告)日：2018-03-01

申请号：US15252592

申请日：2016-08-31

Applicant: ARM LIMITED

Inventor： Saurabh Pijuskumar SINHA ,  Kyungwook CHANG ,  Brian Tracy CLINE ,  Ebbin Raney SOUTHERLAND, JR.

IPC: G06F17/50

Abstract: A method for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.