公开(公告)号：US20150227376A1

公开(公告)日：2015-08-13

申请号：US14596948

申请日：2015-01-14

Applicant: ARM Limited

Inventor： Andreas Due ENGH-HALSTVEDT ,  Ian Victor DEVEREUX ,  David BERMINGHAM ,  Jakob Alex FRIES ,  Oskar Lars FLORDAL

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3869 ,  G06F9/38 ,  G06F9/3816 ,  G06F9/3855 ,  G06F9/3867 ,  G06F12/0855 ,  G06F2212/455

Abstract: A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbours within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.

Abstract translation: 数据处理系统包括用于并行执行多个线程的处理流水线。 问题控制器向处理管道发出线程。 缓存管理器控制在高速缓存内存中发生高速缓存未命中时线程的停止和卸载。 问题控制器根据主序列和导频序列将线程发出到处理流水线。 跟随导频序列，使得导频序列内的线程在主序列内的至少一个给定的时间之前被发送到它们的邻居之前。 给定的时间大致对应于与高速缓存未命中关联的等待时间。 线程可以以对应于像素块的组排列，以在图形处理单元内进行处理。