公开(公告)号：US10983916B2

公开(公告)日：2021-04-20

申请号：US15446235

申请日：2017-03-01

Applicant: ARM Limited

Inventor： Huzefa Moiz Sanjeliwala ,  Klas Magnus Bruce ,  Leigang Kou ,  Michael Filippo ,  Miles Robert Dooley ,  Matthew Andrew Rafacz

IPC: G06F12/00 ,  G06F12/0897 ,  G06F12/0862

Abstract: A data processing apparatus is provided that includes a plurality of storage elements. Receiving circuitry receives a plurality of incoming data beats from cache circuitry and stores the incoming data beats in the storage elements. At least one existing data beat in the storage elements is replaced by an equal number of the incoming data beats belonging to a different cache line of the cache circuitry. The existing data beats stored in said plurality of storage elements form an incomplete cache line.